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On-line digital compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators 级联/spl Sigma//spl Delta/调制器模拟电路缺陷的在线数字补偿
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569394
A. Wiesbuer, G. Temes
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引用次数: 12
All Verilog mixed-signal simulator with analog behavioral and noise models 所有Verilog混合信号模拟器模拟行为和噪声模型
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-01-01 DOI: 10.1109/AMICD.1996.569382
M. Mayes, S. Chin
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引用次数: 22
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