{"title":"级联/spl Sigma//spl Delta/调制器模拟电路缺陷的在线数字补偿","authors":"A. Wiesbuer, G. Temes","doi":"10.1109/AMICD.1996.569394","DOIUrl":null,"url":null,"abstract":"Multi-bit cascaded /spl Sigma//spl Delta/ modulators are known to suffer from performance degradation caused by analog circuit imperfections. In this paper, a method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3/sup rd/-order multi-bit switched-capacitor modulator. Simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity. Realizing the considered modulator without digital compensation would require at least 80 db op-amp gain and capacitor accuracy better than 0.05%, and comparably difficult specifications on op-amp settling. The analog circuit requirements are relaxed by the adaptation to 54 dB op-amp gain, 0.4% capacitor accuracy and 1% op-amp settling, which are readily attainable.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"340 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"On-line digital compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators\",\"authors\":\"A. Wiesbuer, G. Temes\",\"doi\":\"10.1109/AMICD.1996.569394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multi-bit cascaded /spl Sigma//spl Delta/ modulators are known to suffer from performance degradation caused by analog circuit imperfections. In this paper, a method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3/sup rd/-order multi-bit switched-capacitor modulator. Simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity. Realizing the considered modulator without digital compensation would require at least 80 db op-amp gain and capacitor accuracy better than 0.05%, and comparably difficult specifications on op-amp settling. The analog circuit requirements are relaxed by the adaptation to 54 dB op-amp gain, 0.4% capacitor accuracy and 1% op-amp settling, which are readily attainable.\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"340 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.569394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-line digital compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators
Multi-bit cascaded /spl Sigma//spl Delta/ modulators are known to suffer from performance degradation caused by analog circuit imperfections. In this paper, a method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3/sup rd/-order multi-bit switched-capacitor modulator. Simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity. Realizing the considered modulator without digital compensation would require at least 80 db op-amp gain and capacitor accuracy better than 0.05%, and comparably difficult specifications on op-amp settling. The analog circuit requirements are relaxed by the adaptation to 54 dB op-amp gain, 0.4% capacitor accuracy and 1% op-amp settling, which are readily attainable.