级联/spl Sigma//spl Delta/调制器模拟电路缺陷的在线数字补偿

A. Wiesbuer, G. Temes
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引用次数: 12

摘要

众所周知,多位级联/spl Sigma//spl Delta/调制器会因模拟电路缺陷而导致性能下降。本文介绍了一种对有限运放增益和电容失配等线性误差进行自适应数字在线补偿的方法。以两级3/sup /阶多比特开关电容调制器为例,对该方法进行了讨论。仿真结果表明,只需稍微增加硬件复杂度,就可以实现近乎完美的补偿。在没有数字补偿的情况下实现所考虑的调制器将需要至少80 db的运算放大器增益和优于0.05%的电容精度,并且运算放大器的设置规格相对困难。通过适应54 dB运算放大器增益,0.4%电容精度和1%运算放大器沉降,可以轻松实现模拟电路要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On-line digital compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators
Multi-bit cascaded /spl Sigma//spl Delta/ modulators are known to suffer from performance degradation caused by analog circuit imperfections. In this paper, a method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3/sup rd/-order multi-bit switched-capacitor modulator. Simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity. Realizing the considered modulator without digital compensation would require at least 80 db op-amp gain and capacitor accuracy better than 0.05%, and comparably difficult specifications on op-amp settling. The analog circuit requirements are relaxed by the adaptation to 54 dB op-amp gain, 0.4% capacitor accuracy and 1% op-amp settling, which are readily attainable.
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