All Verilog mixed-signal simulator with analog behavioral and noise models

Abstract

This paper describes an all Verilog full chip simulation technique using Verilog macro-models for analog functions and a Verilog noise model simulating the affects of digital cross-talk. Correlation between simulated results and a prototype are shown. The prototype is a 16-bit 1Msample/s pipelined analog-to-digital converter (ADC) with on chip 32-bit micro-controller. Models for operational amplifiers, analog comparators, capacitors, analog switches, and digital cross-talk noise are developed using Verilog syntax. These Verilog macro models are used to build the analog section of the pipelined ADC and are incorporated in a full chip mixed-signal simulation.