{"title":"An efficient and high-performances CMOS op amp with rail-to-rail mode and high CMRR","authors":"G. Klisnick, M. Redon","doi":"10.1109/AMICD.1996.569397","DOIUrl":null,"url":null,"abstract":"In this paper, we present a new structure of a CMOS Op Amp offering high performances differential frequency response with high CMRR, high slew rate and input/output rail-to-rail mode. These performances are due both to a new efficient gain stage with a compact layout and to a simple way to obtain a high CMRR. Simulation experiments have been performed with three different (0.8 /spl mu/m, 1.2 /spl mu/m, 2.4 /spl mu/m) CMOS technologies. In particular for the 0.8 /spl mu/m one, the main performances-under single 5 V power supply are a unity gain bandwidth of 40 MHz, a phase margin of 63 degrees, a slew rate of 60 V//spl mu/s, all performed on heavy load such as 2.5 k/spl Omega//spl par/20 pF. Simulated results have been experimentally confirmed for the 2.4 /spl mu/m CMOS technology for which we have measured a low frequency CMRR of 100 dB.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we present a new structure of a CMOS Op Amp offering high performances differential frequency response with high CMRR, high slew rate and input/output rail-to-rail mode. These performances are due both to a new efficient gain stage with a compact layout and to a simple way to obtain a high CMRR. Simulation experiments have been performed with three different (0.8 /spl mu/m, 1.2 /spl mu/m, 2.4 /spl mu/m) CMOS technologies. In particular for the 0.8 /spl mu/m one, the main performances-under single 5 V power supply are a unity gain bandwidth of 40 MHz, a phase margin of 63 degrees, a slew rate of 60 V//spl mu/s, all performed on heavy load such as 2.5 k/spl Omega//spl par/20 pF. Simulated results have been experimentally confirmed for the 2.4 /spl mu/m CMOS technology for which we have measured a low frequency CMRR of 100 dB.