An efficient and high-performances CMOS op amp with rail-to-rail mode and high CMRR

G. Klisnick, M. Redon
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引用次数: 3

Abstract

In this paper, we present a new structure of a CMOS Op Amp offering high performances differential frequency response with high CMRR, high slew rate and input/output rail-to-rail mode. These performances are due both to a new efficient gain stage with a compact layout and to a simple way to obtain a high CMRR. Simulation experiments have been performed with three different (0.8 /spl mu/m, 1.2 /spl mu/m, 2.4 /spl mu/m) CMOS technologies. In particular for the 0.8 /spl mu/m one, the main performances-under single 5 V power supply are a unity gain bandwidth of 40 MHz, a phase margin of 63 degrees, a slew rate of 60 V//spl mu/s, all performed on heavy load such as 2.5 k/spl Omega//spl par/20 pF. Simulated results have been experimentally confirmed for the 2.4 /spl mu/m CMOS technology for which we have measured a low frequency CMRR of 100 dB.
具有轨对轨模式和高CMRR的高效高性能CMOS运放
在本文中,我们提出了一种新的CMOS运算放大器结构,具有高CMRR,高摆率和输入/输出轨对轨模式的高性能差分频率响应。这些性能是由于一个新的高效增益级与紧凑的布局和简单的方法获得高CMRR。采用三种不同的CMOS技术(0.8 /spl mu/m、1.2 /spl mu/m、2.4 /spl mu/m)进行了仿真实验。特别是对于0.8 /spl mu/m CMOS技术,在单个5 V电源下的主要性能是单位增益带宽为40 MHz,相位余量为63度,转换率为60 V//spl mu/s,所有这些都是在2.5 k/spl ω //spl par/20 pF等重负载下进行的。实验结果证实了2.4 /spl mu/m CMOS技术的模拟结果,我们测量了100 dB的低频CMRR。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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