A. Swaminathan, M. Snelgrove, S. Jantzi, S. Bazarjani
{"title":"用于数字无线电的单片复杂sigma-delta调制器","authors":"A. Swaminathan, M. Snelgrove, S. Jantzi, S. Bazarjani","doi":"10.1109/AMICD.1996.1296589","DOIUrl":null,"url":null,"abstract":"II. Complex Filtering An architecture for a 1.9 GHz PCS receiver is described. This architecture uses a single IF and a Complex Bandpass Sigma-Delta Modulator (BPEAM) to digitize the signal at the IF. This demonstrates the feasibility of this type of modulator in I/Q radios. Image rejection is then done in DSI? A fourth order XA modulator has been realized in a 0.8um BiCMOS process for the receiver. The modulator is clocked at 4MHz, with a SNR of 48dB for an oversampling ratio (OSR) of 200 and has a power dissipation of 15OmW with a 5V supply. Most filters have transfer functions that contain conjugate poles and zeros because they use real coefficients. A complex filter can be designed that has non-conjugate poles and zeros which takes a complex-valued input and gives a complex-valued output [6][7][8]. This makes it particularly useful for I/Q (real/imaginary) radio applications. r i Xre(2) A re (z ) m Yre(2)","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"174 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A monolithic complex sigma-delta modulator for digital radio\",\"authors\":\"A. Swaminathan, M. Snelgrove, S. Jantzi, S. Bazarjani\",\"doi\":\"10.1109/AMICD.1996.1296589\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"II. Complex Filtering An architecture for a 1.9 GHz PCS receiver is described. This architecture uses a single IF and a Complex Bandpass Sigma-Delta Modulator (BPEAM) to digitize the signal at the IF. This demonstrates the feasibility of this type of modulator in I/Q radios. Image rejection is then done in DSI? A fourth order XA modulator has been realized in a 0.8um BiCMOS process for the receiver. The modulator is clocked at 4MHz, with a SNR of 48dB for an oversampling ratio (OSR) of 200 and has a power dissipation of 15OmW with a 5V supply. Most filters have transfer functions that contain conjugate poles and zeros because they use real coefficients. A complex filter can be designed that has non-conjugate poles and zeros which takes a complex-valued input and gives a complex-valued output [6][7][8]. This makes it particularly useful for I/Q (real/imaginary) radio applications. r i Xre(2) A re (z ) m Yre(2)\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"174 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.1296589\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.1296589","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
摘要
2介绍了一种1.9 GHz PCS接收机的结构。该架构使用单个中频和复杂带通Sigma-Delta调制器(BPEAM)在中频处对信号进行数字化。这证明了这种调制器在I/Q无线电中的可行性。然后在DSI中进行图像抑制?采用0.8um BiCMOS工艺实现了接收机的四阶XA调制器。该调制器的时钟频率为4MHz,过采样比(OSR)为200,信噪比为48dB, 5V电源时功耗为15OmW。大多数滤波器都有包含共轭极点和零的传递函数,因为它们使用实系数。可以设计一种具有非共轭极点和零的复滤波器,其输入为复值,输出为复值[6][7][8]。这使得它对I/Q(实/虚)无线电应用特别有用。r i Xre(2) A re(z) m Yre(2)
A monolithic complex sigma-delta modulator for digital radio
II. Complex Filtering An architecture for a 1.9 GHz PCS receiver is described. This architecture uses a single IF and a Complex Bandpass Sigma-Delta Modulator (BPEAM) to digitize the signal at the IF. This demonstrates the feasibility of this type of modulator in I/Q radios. Image rejection is then done in DSI? A fourth order XA modulator has been realized in a 0.8um BiCMOS process for the receiver. The modulator is clocked at 4MHz, with a SNR of 48dB for an oversampling ratio (OSR) of 200 and has a power dissipation of 15OmW with a 5V supply. Most filters have transfer functions that contain conjugate poles and zeros because they use real coefficients. A complex filter can be designed that has non-conjugate poles and zeros which takes a complex-valued input and gives a complex-valued output [6][7][8]. This makes it particularly useful for I/Q (real/imaginary) radio applications. r i Xre(2) A re (z ) m Yre(2)