{"title":"用于带通应用的2路/spl Sigma//spl Delta/调制器","authors":"E. André, D. Morche, F. Balestro, P. Senn","doi":"10.1109/AMICD.1996.569392","DOIUrl":null,"url":null,"abstract":"This article presents a low-power bandpass sigma-delta modulator using a multibit quantizer (9 levels) and switched-capacitor DAC. The circuit is being manufactured in the 0.5 /spl mu/m CMOS technology to operate with a 3.3-/spl nu/ power supply. The sampling frequency Fs=24.576 MHz has been chosen to be equal to 4 times the intermediate frequency fo=6.144 MHz. Computer simulations revealed a SNR=60 dB (10 bits) with a bandwith of 1.536 MHz, that is to say OSR=8. The power consumption is evaluated at 25 mW and the integration surface at about 2 mm/sup 2/. The performance evaluation is based on the test results of a previous circuit designed on the same basis (a 1-bit 4th-order bandpass /spl Sigma//spl Delta/ modulator).","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 2-path /spl Sigma//spl Delta/ modulator for bandpass applications\",\"authors\":\"E. André, D. Morche, F. Balestro, P. Senn\",\"doi\":\"10.1109/AMICD.1996.569392\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a low-power bandpass sigma-delta modulator using a multibit quantizer (9 levels) and switched-capacitor DAC. The circuit is being manufactured in the 0.5 /spl mu/m CMOS technology to operate with a 3.3-/spl nu/ power supply. The sampling frequency Fs=24.576 MHz has been chosen to be equal to 4 times the intermediate frequency fo=6.144 MHz. Computer simulations revealed a SNR=60 dB (10 bits) with a bandwith of 1.536 MHz, that is to say OSR=8. The power consumption is evaluated at 25 mW and the integration surface at about 2 mm/sup 2/. The performance evaluation is based on the test results of a previous circuit designed on the same basis (a 1-bit 4th-order bandpass /spl Sigma//spl Delta/ modulator).\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.569392\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569392","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2-path /spl Sigma//spl Delta/ modulator for bandpass applications
This article presents a low-power bandpass sigma-delta modulator using a multibit quantizer (9 levels) and switched-capacitor DAC. The circuit is being manufactured in the 0.5 /spl mu/m CMOS technology to operate with a 3.3-/spl nu/ power supply. The sampling frequency Fs=24.576 MHz has been chosen to be equal to 4 times the intermediate frequency fo=6.144 MHz. Computer simulations revealed a SNR=60 dB (10 bits) with a bandwith of 1.536 MHz, that is to say OSR=8. The power consumption is evaluated at 25 mW and the integration surface at about 2 mm/sup 2/. The performance evaluation is based on the test results of a previous circuit designed on the same basis (a 1-bit 4th-order bandpass /spl Sigma//spl Delta/ modulator).
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