A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator

Abstract

A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.