{"title":"单回路二阶/spl Delta//spl Sigma/鉴频器","authors":"W. T. Bax, M. Copeland, T. Riley","doi":"10.1109/AMICD.1996.569375","DOIUrl":null,"url":null,"abstract":"A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator\",\"authors\":\"W. T. Bax, M. Copeland, T. Riley\",\"doi\":\"10.1109/AMICD.1996.569375\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.569375\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator
A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.
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