24th International Reliability Physics Symposium最新文献

{"title":"Suppression of Stress Induced Aluminum Void Formation","authors":"H. Koyama, Y. Mashiko, T. Nishioka","doi":"10.1109/IRPS.1986.362107","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362107","url":null,"abstract":"It is found that aluminum void formation can be suppressed by mercury light irradiation of plasma enhanced chemical vapor deposition silicon nitride filmn coatings. Light beam induced stress relaxation of the SiN film is responsible for the suppression. We believe that presence of hydrogen in the aluminum lattice would create micro voids which aggregate into aluminum voids by the applied stress of the silicon nitride film.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122548930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Input ESD Protection Networks for Fineline NMOS - Effects of Stressing Waveform and Circuit Layout","authors":"L. Dechiaro, S. Vaidya, R. G. Chemelli","doi":"10.1109/IRPS.1986.362135","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362135","url":null,"abstract":"Human Body Model (HBM) and Charged Device Model (CDM) electrostatic discharge (ESD) stressing have been utilized to evaluate the susceptibility of input protection circuits on a fineline NMOS test chip. Failure analysis results and failure thresholds are reported as a function of local protection device parameters such as channel length and width and global layout variables such as power supply routing and circuit placement. It is demonstrated that the susceptibility to HBM stressing is determined primarily by protection device geometry. Failures occur by localized heating and filamentation across the channel. CDM failures, on the other hand, are sensitive to both local and global chip layout and occur primarily by damage to the thin gate oxide. In addition, CDM failure thresholds are much lower than those for the HBM case. These results are analyzed and a theoretical model for CDM failure developed on the basis of differences in protection device capacitance ratio and the critical charge for oxide breakdown due to Fowler-Nordheim tunneling.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132662397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gradual Degradation of GaAs FETs Under Normal Operation","authors":"M. Millea","doi":"10.1109/IRPS.1986.362122","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362122","url":null,"abstract":"The gradual degradation of low-noise and power GaAs FETs under normal operating conditions has been investigated. The degradation of the drain current under both low and normal biasing was monitored for low-noise devices, but only the degradation of the drain resistance was monitored for power GaAs FETs. Using elevated temperatures to stabilize devices and assuming a single monotonically decreasing failure mode, it is relatively simple to determine the device's long-term reliability within several days of operating at normal temperatures of 100°C or lower. This is accomplished by observing a sufficiently low degradation rate, which, when extrapolated to the desired end-of-life, yields an acceptable low longterm degradation estimation. To minimize the risk associated with the possible existence of compensating gradual degradation modes, the gradual degradation of devices is examined against a second gradual degradation failure criterion, which is based on the device having a sufficient low-degradation second derivative. Fulfilling the second-order failure criterion is more difficult to demonstrate and is the main focus of this investigation.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133057598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-Mechanical Cycling Behavior of Al Thin-Film Metallization","authors":"H. Hieber, T. Simon","doi":"10.1109/IRPS.1986.362142","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362142","url":null,"abstract":"Al-based thin-film metallizations are used as electrical interconnections in integrated circuits and in most of discrete, active components L1]. After deposition at temperatures T between 400 and 450K by evaporat ion or sputtering, different thermal treatments work on the metallizations: The baking of photoresists and the ion etching upto T 320K, the alloying of ohmic contacts with Si upto T-720K, the die bonding and the thermosonic wire bonding at T-500K, the moulding of the encapsulation at T-430K. After the production steps the components are subject to softsoldering on printed-circuit boards with T>520K and thermal cycling during the application between T-220K and T=500K. The time st eps at the named temperatures range between few and 103s, the thermal rates get up to T102Ks-1. Due to the filmn thickness h'1i, the grain sizes d.,5pm and the concentration of lattice defects the thermal treatments cause changes in the film structure and local chemical composition. As the filrns and Si wafers have different coefficients of thermal expansion aF and cr.,.and the substrates are much thicker and mechanically rnore rigid than the films, the films are subjected to thermal compressive or tensile strains. The induced stresses exceed the yield point of the films. The straln relaxation of the metal films during continuous changes in T is explained in terms of diffusional creep [2], of dislocation slip [13] and by comparison of the different driving forces working on mobile grain boundaries and vacancies in the grains [4]. Metals with low stacking fault energy show discontinuous grain growth [5]. Al-based films exhibit the formation of hillocks [6,7] which is not yet explained quantitatively. The purpose of this paper is to learn the kinetics of partially reversible and of irreversible defect reaction mechanisms in Al-based thin-film metallizations on substrates from the measurement of stress relaxation during thermomechanical treatments. It will be shown that the sequence of diffusional creep and of the growth of single grains are sensitively dependent on the thermal and mechanical history. Changes in dc resistance indicate the production of lattice defects under tensile stress and the absorption under compressive stress. initial grain sizes are (100.. . 300)nm of the evaporated and (1...3)pm foir the sputtered films measured by line interception of TEM micrographs. The lateral macrostresses in the films are >1.OMPa at 300K measured by the substrate curvature before and after the removal of the Al films by chemical etching.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126185594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Method for Measuring Nonuniformities in Metallization Temperatures of an Operating Integrated Circuit","authors":"R. Clinton","doi":"10.1109/IRPS.1986.362106","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362106","url":null,"abstract":"A nonuniform temperature distribution was observed along the metallization and on the top surface of an integrated circuit. Very small latex SEM calibration spheres were distributed over the circuit, and their changes of shape and contrast, due to melting, allowed us to discern hotter and cooler regions on the chip. Much of what was observed seemed to indicate that electromigration can take place at a relatively low temperature, around 113°C or less. Further discussion of the thermal calibration of the spheres, effects of the surface, and the effects of the vacuum is also given. Various difficulties involved with the technique and some proposals to overcome them are given as well.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SEM Studies of Time Evolution and Sensitivity of Latch-up in CMOS ICs","authors":"C. Canali, F. Fantini, M. Giannini, A. Snin, E. Zanoni","doi":"10.1109/IRPS.1986.362137","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362137","url":null,"abstract":"An electron beam testing system has been developed for a complete and detailed analysis of latch-up in CMOS integrated circuits. The technique allows: the identification of latch-up current paths in steady-state condition; the observation of the time evolution of latch-up from the firing event to the final condition; the measurement of the local latch-up sensitivity of the various parts of the circuit to an external current source.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121630078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hot Electron Induced Retention Time Degradation in MOS Dynamic RAMs","authors":"E. Cahoon, K. Thornewell, P. Tsai, T. Gukelberger, J. Sylvestri, J. Orro","doi":"10.1109/IRPS.1986.362133","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362133","url":null,"abstract":"Hot electron induced MOSFET instabilities have been found to significantly degrade the retention time of dynamic RAMs. Failure is due to the effect of increased subthreshold leakage on balanced sense nodes. Plasma nitride passivations greatly increase the degradation rate. The complex synergism between device degradation and DRAM parametric shift demonstrates the necessity of accelerated stress of functional modules.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116150274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Investigation of 1 Micron Depletion Mode IC MESFETs","authors":"D. Ogbonnah, A. Fraser","doi":"10.1109/IRPS.1986.362123","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362123","url":null,"abstract":"A 1.6 eV activation energy has been observed for gate degradation of GaAs MESFETs fabricated with a commercially available 1 micron depletion mode IC process. Data from deep level transient spectroscopy (DLTS) and capacitance-voltage (C-V) measurements are consistent with a failure mechanism of gate metal interdiffusion into GaAs resulting in a decrease of channel thickness. The median life at 290 °C channel temperature (TCH) was 80 hours, with a lognormal sigma of 0.7. Using these values, the projected FET failure rate is less than 0.01%/l000 hours (100 FIT) during the first million hours of life at TCH= 150 °C.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ESD Protection Reliability in 1μM CMOS Technologies","authors":"C. Duvvury, R. A. McPhee, D. Baglee, R. Rountree","doi":"10.1109/IRPS.1986.362134","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362134","url":null,"abstract":"The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature Dependence of CMOS Device Reliability","authors":"C. Yao, Joseph Thou, R. Cheung, H. Chan","doi":"10.1109/IRPS.1986.362130","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362130","url":null,"abstract":"This paper presents experimental results on the temperature dependence of CMOS device reliability in topological scaling. The latch-up characteristics as functions of temperature, substrate material, and device geometry are reported based on a twin-tub CMOS technology. The trade-off between the advantage of a higher device transconductance in scaled CMOSFET's and the associated reliability constraints due to the hot-carrier-induced device degradation is studied in a wide temperature range. The n-channel LDD MOSFET lifetime is observed to follow t = (A/Id) (Isub/Id)¿2.7 from room temperature to 77 K, where A is a temperature-dependent coefficient with an activation energy of 39 mev. The temperature dependence of the generation of the oxide charge is described. A correlation between the positive charge generated at high injection level and the oxide breakdown is identified.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129872166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}