{"title":"Electromigration in Titanium Doped Aluminum Alloys","authors":"J. Towner, Albertus C. Dirks, Tien Tien","doi":"10.1109/IRPS.1986.362104","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362104","url":null,"abstract":"Homogeneous films of titanium-doped aluminum and aluminum-1% silicon were evaluated for possible application as interconnects in integrated circuits. Titanium concentration was systemnatically varied in the range of 0 to 1.2 wt.%. Electromigration behavior was studied for each film composition as a function of temperature. Significant differences were found between the binary and ternary alloys, corresponding to differences in the film microstructure.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127091391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Field and Temperature Dependent Life-Time Limiting Effects of Metal-GaAs Interfaces of Device Structures Studied by XPS and Electrical Measurements","authors":"J. Wurfl, H. Hartnagel","doi":"10.1109/IRPS.1986.362124","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362124","url":null,"abstract":"Typical Schottky contacts for GaAs devices such as Al and TiPtAu metallizations have been accelerated-stress tested under bias at room temperature and at temperatures up to 250° C. The influence of these stress tests on the interface properties were studied by XPS sputter profiling and correlated with electrical measurements. Concerning Al-contacts it has been found that bias-stressing results in a structural change of the Al layer and that the oxygen concentration at the Al-GaAs transition depends both on the polarity of bias stressing and on the GaAs surface treatment before Al-metallization. These effects are quite pronounced even at room temperature. TiPtAu contacts are stable at room temperature over the period of investigation (200 h) but at elevanted temperatures (200° C) a GaAs diffusion into Ti and a subsequent Ti diffusion into Ga vacancies could be observed. This results in a catastrophic bias dependent degradation of the I/V characteristics.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122961329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Power Pulse Reliability of GaAs Power FETs","authors":"W. Anderson, F. Buot, A. Christou, Y. Anand","doi":"10.1109/IRPS.1986.362125","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362125","url":null,"abstract":"A study was made of degradation and burnout of GaAs power FETs resulting from high power RF pulses on the gate while operating at X-band. Burnout power per unit gate width (W/mm) was found to be an important parameter. The failure mechanisms were found to be subsurface burnout and high-field induced metal bridging from the gate to the source or drain. Numerical simulations show high current density transients at the gate and hot electron thermal transients at the source and drain. Hot electrons are created near the edges of the gate and at the source and drain regions by a high power pulse. It is suggested that these lead to degradation by recoil-enhanced interdiffusion at the gate and thermally-induced metal-GaAs interdiffusion, mainly at the source and drain. If such degradation progresses to the point where filamentary metal-GaAs interdiffusions reach the substrate/active channel interface, subsurface burnout is initiated by thermal runaway.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of Ceramic Packaging Anneal on the Reliability of Al Interconnects","authors":"M. Lin, J. Yue","doi":"10.1109/IRPS.1986.362128","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362128","url":null,"abstract":"Experimental results show conclusive evidence that stress induced metal voids and Si nodules (both of which originate during wafer processing) grow significantly after Ceramic Packaging (CDIP) glass sealing anneal. Furthermore, the growth of a metal void is almost always accompanied by Si precipitation in its immediate neighborhood. The combination of a metal void and an adjacent silicon nodule was observed to significantly reduce the net metal line cross-sectional area and is highly undesirable for interconnect reliability. In this paper the above phenomenon is fully explained and the effects of COIP anneal temperature profiles are examined.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121584677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Layer Damage Model for Calculating Thermal Fatigue Lifetime of Power Devices","authors":"Gao Guang-bo, C. An, Gui Xiang","doi":"10.1109/IRPS.1986.362114","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362114","url":null,"abstract":"Based on the experimental data during device power cycling, the mechanical behavior of solder material, and by introducing a new concept \"layer damage factor ß\", the authors have proposed a layer damage model for calculating thermal fatique lifetime of power devices. The model can be used in estimating fatique lifetime, evaluating soldering quality, obtaining accelerated lifetime plot, designing chip backside metallizations, etc. Experimental results have been shown to support the theory.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Distribution of Electromigration Failures","authors":"D. Lacombe, Earl L. Parks","doi":"10.1109/IRPS.1986.362103","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362103","url":null,"abstract":"This paper presents the results of an evaluation of the statistical distribution of electromigration test failures. Large scale life tests were carried out and the natujre of the failure distributions were determined for lines of varying length and width. In all cases, the distribution were found to be log-normal down to at least the 0.3% failure point. Possible reasons for these results and their implications with regard to the design of a cost effective electromigration testing program are discussed.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130716089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power GaAs FET RF Life Test using Temperature-Compensated Electrical Stressing","authors":"K. Russell, J. Dhiman","doi":"10.1109/IRPS.1986.362126","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362126","url":null,"abstract":"GaAs FETs were aged in RF operation, while keeping the electrical stress on the WETs like that in a typical application. Lifetimes measured were significantly lower than those predicted by life tests using dc bias only. Significant dependence of lifetimes upon the wafer process lot was found. Voltage screening did not provide more reliable devices.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131294255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault Contrast: A New Voltage Contrast VLSI Diagnosis Technique","authors":"A. Stivers, D. C. Ferguson","doi":"10.1109/IRPS.1986.362119","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362119","url":null,"abstract":"Fault contrast is a differential analog technique that yields high-quality voltage contrast images of integrated circuit (IC) pass vs. fail operation. Fault contrast is applicable where the IC failure mode is sensitive to an external parameter, e.g. clock frequency or supply voltage. Fault contrast requires only simple and inexpensive analog signal processing. We demonstrate fault contrast with an analysis of an Intel 80286 microprocessor failure.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Ishiuchi, T. Watanabe, T. Tanaka, K. Kishi, M. Ishikawa, N. Goto, K. Kohyama, H. Noji, O. Ozawa
{"title":"Soft Error Rate Reduction in Dynamic Memory with Trench Capacitor Cell","authors":"H. Ishiuchi, T. Watanabe, T. Tanaka, K. Kishi, M. Ishikawa, N. Goto, K. Kohyama, H. Noji, O. Ozawa","doi":"10.1109/IRPS.1986.362139","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362139","url":null,"abstract":"Alpha-particle-induced soft error rate of dynamic memory with trench capacitor cell has been studied experimentally. Both the bit line mode and the cell mode of the soft error rate can be effectively reduced utilizing a p-well structure on p-type substrate. The reduction ratio is about 1/200 or less.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127473264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Device Leakage Investigation Using Fluorescent Microthermography","authors":"H. Cong, K. Cunniff, J. Tyson, P. Kolodner","doi":"10.1109/IRPS.1986.362127","DOIUrl":"https://doi.org/10.1109/IRPS.1986.362127","url":null,"abstract":"We report an investigation of the buffer leakages on VLSI devices using a fundamentally new thermal imager based on the fluorescence of Europium Thenoyltrifluoroacetonate. The use of the imager greatly facilitates the task of finding the spots of high leakage current and simplifies the follow-up analysis work for the identification of device defects. Correlation between the defects and the current-voltage characteristics of the buffer circuits has been found. This correlation and the origins of the defects are discussed.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"5 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}