Soft Error Rate Reduction in Dynamic Memory with Trench Capacitor Cell

H. Ishiuchi, T. Watanabe, T. Tanaka, K. Kishi, M. Ishikawa, N. Goto, K. Kohyama, H. Noji, O. Ozawa
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引用次数: 2

Abstract

Alpha-particle-induced soft error rate of dynamic memory with trench capacitor cell has been studied experimentally. Both the bit line mode and the cell mode of the soft error rate can be effectively reduced utilizing a p-well structure on p-type substrate. The reduction ratio is about 1/200 or less.
沟槽电容单元动态存储器的软错误率降低
实验研究了沟槽电容电池动态记忆的软错误率。利用p型衬底上的p阱结构,可以有效地降低软误码率的位线模式和单元模式。减速比约为1/200或更小。
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