2012 IEEE International Test Conference最新文献_第5页

Low power test application with selective compaction in VLSI designs 在VLSI设计中具有选择性压实的低功耗测试应用

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401532

Dariusz Czysz, J. Rajski, J. Tyszer

引用次数: 8

Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit 复杂图形处理单元用高速I/O接口故障分级方法

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401585

Animesh Khare, P. Kishore, S. Reddy, K. Rajan, A. Sanghani

引用次数: 1

Low-power SRAMs power mode control logic: Failure analysis and test solutions 低功耗sram电源模式控制逻辑:故障分析和测试解决方案

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401578

L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine

引用次数: 9

Making predictive analog/RF alternate test strategy independent of training set size 制定独立于训练集大小的预测模拟/射频替代测试策略

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401560

H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzérho, O. Potin, M. Renovell

引用次数: 42

Integrated optimization of semiconductor manufacturing: A machine learning approach 半导体制造的集成优化:一种机器学习方法

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401531

Nathan Kupp, Y. Makris

{"title":"Integrated optimization of semiconductor manufacturing: A machine learning approach","authors":"Nathan Kupp, Y. Makris","doi":"10.1109/TEST.2012.6401531","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401531","url":null,"abstract":"As semiconductor process nodes continue to shrink, the cost and complexity of manufacturing has dramatically risen. This manufacturing process also generates an immense amount of data, from raw silicon to final packaged product. The centralized collection of this data in industry information warehouses presents a promising and heretofore untapped opportunity for integrated analysis. With a machine learning-based methodology, latent correlations in the joint process-test space could be identified, enabling dramatic cost reductions throughout the manufacturing process. To realize such a solution, this work addresses three distinct problems within semiconductor manufacturing: (1) Reduce test cost for analog and RF devices, as testing can account for up to 50% of the overall production cost of an IC; (2) Develop algorithms for post-production performance calibration, enabling higher yields and optimal power-performance; and, (3) Develop algorithms for spatial modeling of sparsely sampled wafer test parameters. Herein these problems are addressed via the introduction of a model-view-controller (MVC) architecture, designed to support the application of machine learning methods to problems in semiconductor manufacturing. Results are demonstrated on a variety of semiconductor manufacturing data from TI and IBM.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

FALCON: Rapid statistical fault coverage estimation for complex designs 用于复杂设计的快速统计故障覆盖估计

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401584

S. Mirkhani, J. Abraham, T. Vo, H. Jun, B. Eklow

引用次数: 8

On modeling faults in FinFET logic circuits 论FinFET逻辑电路中的建模故障

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401565

Yuxi Liu, Q. Xu

引用次数: 48

Board assisted-BIST: Long and short term solutions for testpoint erosion — Reaching into the DFx toolbox 电路板辅助- bist:测试点侵蚀的长期和短期解决方案-进入DFx工具箱

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401572

Z. Conroy, James J. Grealish, H. Miles, Anthony J. Suto, A. Crouch, S. Meyers

引用次数: 7

Hybrid selector for high-X scan compression 高x扫描压缩的混合选择器

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401558

P. Wohl, J. Waicukauski, Frederic Neuveux, J. E. Colburn

引用次数: 10

On pinpoint capture power management in at-speed scan test generation 高速扫描测试生成中的精确捕获电源管理

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401548

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, Laung-Terng Wang

{"title":"On pinpoint capture power management in at-speed scan test generation","authors":"X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, Laung-Terng Wang","doi":"10.1109/TEST.2012.6401548","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401548","url":null,"abstract":"This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional switching activity), or cold (with excessively-low switching activity). Then, X-restoration/X-filling-based rescue is conducted on the test vector to reduce switching activity around hot paths. If the rescue is insufficient to turn a hot path into a warm path, mask is then conducted on expected test response data to instruct the tester to ignore the potentially-false test response value from the hot path, thus achieving guaranteed capture power safety. Finally, X-restoration/X-filling-based warm-up is conducted on the test vector to increase switching activity around cold paths for improving their small-delay test capability. This novel approach of pinpoint capture power management has significant advantages over the conventionalapproachofglobalcapturepower management, as demonstrated by evaluation results on large ITC'99 benchmark circuits and detailed path delay analysis.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132207644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25