2012 IEEE International Test Conference最新文献_第7页

Modeling, verification and pattern generation for reconfigurable scan networks 可重构扫描网络的建模、验证和模式生成

2012 IEEE International Test Conference Pub Date : 2012-11-01 DOI: 10.1109/TEST.2012.6401555

R. Baranowski, M. Kochte, H. Wunderlich

{"title":"Modeling, verification and pattern generation for reconfigurable scan networks","authors":"R. Baranowski, M. Kochte, H. Wunderlich","doi":"10.1109/TEST.2012.6401555","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401555","url":null,"abstract":"Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

A memory yield improvement scheme combining built-in self-repair and error correction codes 一种结合内置自修复和纠错码的存储器良率改进方案

2012 IEEE International Test Conference Pub Date : 2012-11-01 DOI: 10.1109/TEST.2012.6401576

Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, C. Peng, Min-Jer Wang

{"title":"A memory yield improvement scheme combining built-in self-repair and error correction codes","authors":"Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, C. Peng, Min-Jer Wang","doi":"10.1109/TEST.2012.6401576","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401576","url":null,"abstract":"Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this paper, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement. Many modern memories are equipped with ECC in addition to BISR. We evaluate the back-end flow that combines both ECC and BIRA to determine whether yield can be improved by proper sequencing of the two steps. We also collect and identify important failure patterns and their distributions from over 100,000 sample memory instances, which are used to enhance the EEMR scheme that incorporates ECC. As ECC is failure pattern sensitive, careful evaluation from realistic failure bitmaps is necessary. We also verify the feasibility of implementing the proposed EEMR scheme by real test data. Experimental results from industrial 4Mb memory instances show that the proposed EEMR scheme gains over 2% instance yield on average, as compared with the traditional scheme. We also investigate the reliability of the EEMR scheme with different ECC specifications and BIRA algorithms.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115641948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

A built-in self-test scheme for 3D RAMs 内置的3D ram自测方案

2012 IEEE International Test Conference Pub Date : 2012-11-01 DOI: 10.1109/TEST.2012.6401579

Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, D. Kwai, Yung-Fa Chou, Cheng-Wen Wu

引用次数: 9

Real-time testing method for 16 Gbps 4-PAM signal interface 16gbps 4-PAM信号接口的实时测试方法

2012 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2012.6401524

M. Ishida, K. Ichiyama, D. Watanabe, M. Kawabata, T. Okayasu

{"title":"Real-time testing method for 16 Gbps 4-PAM signal interface","authors":"M. Ishida, K. Ichiyama, D. Watanabe, M. Kawabata, T. Okayasu","doi":"10.1109/TEST.2012.6401524","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401524","url":null,"abstract":"This paper proposes a method for testing a device with multi-level signal interfaces. This method utilizes multi-level drivers that generate multi-level signals and multi-level comparators that are based on a new concept. The multi-level drivers can test the voltage noise tolerance of a receiver device with multi-level signal interfaces. The multi-level comparators realize real-time functional testing of a multi-level signal with the same number of comparators as a conventional test system, by changing the threshold voltage levels dynamically in response to the expected values of a signal under test. This dynamic threshold comparator concept is suitable for a system testing a high-speed multi-level signal. This method is also scalable for an increase in the number of voltage levels such as 8-PAM and 16-PAM signals. In addition, with the proposed method, the testing of a signal having emphasis/ de-emphasis can be realized, and improved testing of the digital modulation signal such as by QAM can be expected. Experimental results are discussed with a prototype circuit that demonstrates the proposed concept applied to a 16 Gbps 4-PAM Test System. Applications of the proposed method are also discussed.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7