{"title":"Adaptive test selection for post-silicon timing validation: A data mining approach","authors":"Ming Gao, Peter Lisherness, K. Cheng","doi":"10.1109/TEST.2012.6401540","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401540","url":null,"abstract":"Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow via bug root-cause analysis. However, the value of this silicon data for helping further improvement of the post-silicon validation process has been largely overlooked. In this paper, we propose an adaptive test selection method to progressively tune the validation plan using knowledge automatically mined from the bug sightings during post-silicon validation. Experimental results demonstrate that the proposed fault-model-free data mining approach can prioritize those tests capable of uncovering more silicon timing errors, resulting in significant reduction of validation time and effort.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123429063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaoxiao Wang, Dat Tran, S. George, L. Winemberg, N. Ahmed, Steve Palosh, Allan Dobin, M. Tehranipoor
{"title":"Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements","authors":"Xiaoxiao Wang, Dat Tran, S. George, L. Winemberg, N. Ahmed, Steve Palosh, Allan Dobin, M. Tehranipoor","doi":"10.1109/TEST.2012.6401593","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401593","url":null,"abstract":"As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and EDA industries, since a significantly increased mismatch is emerging between modeled and actual silicon behavior. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch. This paper presents a standard-cell-based, novel, and accurate sensor for reliability analysis of digital ICs (Radic), in order to better understand the characteristics of gate/path aging and process variations' impact on timing performance. The Radic sensor performs aging, flip-flop (FF) metastability window and variation measurements on-chip. This sensor has been fabricated in a floating gate Freescale SOC in very advanced technology. The measurement results demonstrate that the resolution is better than 0.1ps, and the accuracy is kept throughout aging/process variation. Furthermore, reliability and FF metastability measurements are performed using the proposed sensor. The measurement results agree with the existing models.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor","authors":"T. McLaurin, F. Frederick, R. Slobodnik","doi":"10.1109/TEST.2012.6401534","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401534","url":null,"abstract":"The DFT and test challenges faced, and the solutions applied, to the Cortex-A15 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT flow that addresses multiple identical CPUs that will ultimately end up in many different design and test environments. We describe work done with EDA vendors to ensure that all mutual customers are able to implement this flow. In addition, this paper discusses the use of the ARM MBIST standardized interface in conjunction with a 3rd party MBIST controller for the first time. We collaborated closely with the 3rd party tool company and met all of the challenges to get this first time flow and tool capability working successfully on silicon.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"80 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114098547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Altet, D. Mateo, D. Gómez, X. Perpiñà, M. Vellvehí, X. Jordà
{"title":"DC temperature measurements for power gain monitoring in RF power amplifiers","authors":"J. Altet, D. Mateo, D. Gómez, X. Perpiñà, M. Vellvehí, X. Jordà","doi":"10.1109/TEST.2012.6401589","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401589","url":null,"abstract":"In this paper we demonstrate that the steady state temperature increase due to the power dissipated by the circuit under test can be used as observable to test the gain of a 2GHz linear class A Power Amplifier. As a proof of concept, we use two strategies to monitor the temperature: a temperature sensor embedded within the same silicon die, which can be used for a BIST approach, and an Infra Red camera, with applications to failure analysis and product debugging.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121646815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On efficient silicon debug with flexible trace interconnection fabric","authors":"Xiao Liu, Q. Xu","doi":"10.1109/TEST.2012.6401539","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401539","url":null,"abstract":"Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of “key” signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug run. However, both kinds of trace interconnection fabrics have limitations. On one hand, with MUX-based fabric, the visibility of the circuit is limited and it requires many debug runs to locate errors. On the other hand, with XOR-based fabric, typically clean “golden vectors” (i.e, without unknown bits) are required so that signatures are not corrupted. In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114720640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dubois, E. Foucauld, C. Mounet, S. Dia, Cedric Mayor
{"title":"A frequency measurement BIST implementation targeting gigahertz application","authors":"M. Dubois, E. Foucauld, C. Mounet, S. Dia, Cedric Mayor","doi":"10.1109/TEST.2012.6401588","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401588","url":null,"abstract":"In this paper we present a Built-In Self-Test (BIST) technique to measure the natural resonance frequency of oscillators which are design to set a much higher than the working speed of most of the current Automated Test Equipment (ATE). Based on an asynchronous counter, the BIST answers by a digital output code proportional to the frequency of the oscillator under test. The efficiency of the suggested BIST is demonstrated on an ultra wideband transceiver, which communication frequency range si set in a band from 7.25GHz to 8.5GHz.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134455735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Algorithm for dramatically improved efficiency in ADC linearity test","authors":"Zhongjun Yu, Degang Chen","doi":"10.1109/TEST.2012.6401561","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401561","url":null,"abstract":"For high performance analog and mixed-signal products, production test is a significant contributor to the recurring manufacturing cost. For high resolution ADCs, the cost of build can be dominated by test cost, of which linearity test cost is often the largest component. This paper introduces a new algorithm that dramatically reduces ADC linearity test cost. The algorithm takes a system identification approach using a segmented non-parametric model that captures both linear errors (mismatches, etc.) and truly nonlinear errors (voltage coefficients, etc.). By avoiding the gross inefficiencies inherent in conventional linearity test solutions, the new algorithm is able to reduce the required test data by a factor of over 100. The algorithm works for various types of ADCs, including SARs and pipelines. Simulation results and measurements against the gold standard servo-loop test validate the accuracy of the new solution. Results from multiple case studies involving both good and poor ADCs demonstrate that the new method achieved several times better precision than standard histogram test, while using two orders of magnitude less test data and hence test time.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133778801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, F. Javaheri, Z. Navabi
{"title":"BS 1149.1 extensions for an online interconnect fault detection and recovery","authors":"Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, F. Javaheri, Z. Navabi","doi":"10.1109/TEST.2012.6401583","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401583","url":null,"abstract":"Loss of signal integrity in today's deep sub-micron designs puts communication links at a higher risk of permanent or more frequent intermittent faults. This results in performance and reliability reduction. This paper presents an online interconnect BIST method that applies to a hybrid serial/parallel communication scheme. The proposed BIST method is implemented by a simple extension to the boundary scan standard, which facilitates online testing methodology with negligible hardware overhead. The online hardware works in the idle state of the Boundary Scan TAP controller. The proposed method includes fault detection and diagnosis phases. Moreover, for error handling, it uses the same test hardware added to the communication interface. It effectively reuses the existing boundary scan structure to act as a signature generator, an error detector and locater for testing interconnects, and an error handling mechanism. Our method can detect about 90% of the interconnect faults after six block transfers.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117226822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-chip diagnosis for early-life and wear-out failures","authors":"Matthew Beckler, R. D. Blanton","doi":"10.1109/TEST.2012.6401580","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401580","url":null,"abstract":"One approach for achieving integrated-system robustness centers on performing test during runtime, identifying the location of any faults (or potential faults), and repairing or avoiding the affected portion of the system. Fault dictionaries can be used to locate faults but conventional approaches require significant memory storage and are therefore limited to simplistic fault types. To overcome these limitations, three contributions are made that include: (i) enhancement of an unspecified transition fault model (called here the transition-X fault model, or TRAX for short) for capturing the misbehaviors expected from scaled technologies, (ii) development of a new type of hierarchical dictionary that only localizes to the level of repair or fault avoidance, and (iii) the design of a scalable architecture for retrieving and using the hierarchical dictionary for performing on-chip diagnosis. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Moreira, Marc Moessinger, Koji Sasaki, Takayuki Nakamura
{"title":"Driver sharing challenges for DDR4 high-volume testing with ATE","authors":"J. Moreira, Marc Moessinger, Koji Sasaki, Takayuki Nakamura","doi":"10.1109/TEST.2012.6401542","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401542","url":null,"abstract":"The need for larger and faster memories has been a constant requirement in the last decades together with keeping memory costs constant or lower. This presents a significant challenge for cost effective memory testing, not only because of the increased data rates but also the pressure to keep memory testing costs down. This paper addresses one of these challenges, which is the development of driver-sharing designs to allow the development of DDR test solutions with a high number of sites. This paper will describe in detail the challenges that high-volume ATE testing of DDR4 presents in regard to driver sharing, allowing the test engineer to better grasp the problems associated with DDR4 high-volume ATE testing.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130249081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}