Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, S. Sunter
{"title":"A unified method for parametric fault characterization of post-bond TSVs","authors":"Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, S. Sunter","doi":"10.1109/TEST.2012.6401566","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401566","url":null,"abstract":"A TSV in a 3D IC could suffer from two major types of parametric faults - a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"91 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114091679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Sumikawa, J. Tikkanen, Li-C. Wang, L. Winemberg, M. Abadir
{"title":"Screening customer returns with multivariate test analysis","authors":"N. Sumikawa, J. Tikkanen, Li-C. Wang, L. Winemberg, M. Abadir","doi":"10.1109/TEST.2012.6401547","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401547","url":null,"abstract":"This work studies the potential of capturing customer returns with models constructed based on multivariate analysis of parametric wafer sort test measurements. In such an analysis, subsets of tests are selected to build models for making pass/fail decisions. Two approaches are considered. A preemptive approach selects correlated tests to construct multivariate test models to screen out outliers. This approach does not rely on known customer returns. In contrast, a reactive approach selects tests relevant to a given customer return and builds an outlier model specific to the return. This model is applied to capture future parts similar to the return. The study is based on test data collected over roughly 16 months of production for a high-quality SoC sold to the automotive market. The data consists of 62 customer returns belonging to 52 lots. The study shows that each approach can capture returns not captured by the other. With both approaches, the study shows that multivariate test analysis can have a significant impact on reducing customer return rates especially during the later period of the production.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131167480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Capacitive sensing testability in complex memory devices","authors":"K. Parker","doi":"10.1109/TEST.2012.6401570","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401570","url":null,"abstract":"Printed circuit boards (PCB) with soldered-down arrays of advanced memory devices are growing more common and present a class of difficult testing problems to PCB manufacturing. With the large memory capacities now available, memory expansion connectors are less necessary, and many products have reduced form factors (thinness) that means upright memory DIMM arrays are being phased out. When memory devices are soldered down, they become part of the board test problem, where in the past it was only necessary to test the empty sockets that would later be populated with memory. This paper discusses a Design-for-Test (DFT) technology that can be easily applied to memory devices which is independent of the silicon, and only impacts the design of the package the memory is placed within. This means DFT can be retrofitted to memories already in production without a costly silicon design change.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114256100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Spatial estimation of wafer measurement parameters using Gaussian process models","authors":"Nathan Kupp, K. Huang, J. Carulli, Y. Makris","doi":"10.1109/TEST.2012.6401545","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401545","url":null,"abstract":"In the course of semiconductor manufacturing, various e-test measurements (also known as inline or kerf measurements) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites, and include a variety of measurements that characterize the wafer's position in the process distribution. However, these measurements are often only used for wafer-level characterization by process and test teams, as the sampling can be quite sparse across the surface of the wafer. In this work, we introduce a novel methodology for extrapolating sparsely sampled e-test measurements to every die location on a wafer using Gaussian process models. Moreover, we introduce radial variation modeling to address variation along the wafer center-to-edge radius. The proposed methodology permits process and test engineers to examine e-test measurement outcomes at the die level, and makes no assumptions about wafer-to-wafer similarity or stationarity of process statistics over time. Using high volume manufacturing (HVM) data from industry, we demonstrate highly accurate cross-wafer spatial predictions of e-test measurements on more than 8,000 wafers.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122181736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction","authors":"Motoo Ueda, Shinichi Ishikawa, Masaru Goishi, Satoru Kitagawa, Hiroshi Araki, Shuichi Inage","doi":"10.1109/TEST.2012.6401590","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401590","url":null,"abstract":"This paper introduces new capability on System on a Chip (SoC) ATE, called \"Functional Test Abstraction (FTA)\", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A dynamic programming solution for optimizing test delivery in multicore SOCs","authors":"Mukesh Agrawal, Michael Richter, K. Chakrabarty","doi":"10.1109/TEST.2012.6401535","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401535","url":null,"abstract":"We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization. Test-time minimization for grid-based NOCs is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. The proposed method yields high-quality results that are comparable to integer linear programming (ILP), but unlike ILP, it is scalable to large SOCs with many cores. We present results on synthetic NOC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127201675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design validation of RTL circuits using evolutionary swarm intelligence","authors":"Min Li, K. Gent, M. Hsiao","doi":"10.1109/TEST.2012.6401556","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401556","url":null,"abstract":"In this paper, we present BEACON, a Branch-oriented Evolutionary Ant Colony OptimizatioN method which is a bio-inspired meta-heuristic for design validation and functional test generation. BEACON combines an evolutionary search technique with Ant Colony Optimization (ACO) for improved search capability. BEACON first cross-compiles the Verilog circuit source to a C++ base for fast simulation. Then, it profiles the code, keeping track of each branch and the number of times it has been visited in a database. Branch coverage provides a very useful metric for exploring the design, especially visiting the most critical states, including corner states, in the design. At 100% branch coverage, we can conclude that every control state described in the RTL has been visited. Thus, during execution, BEACON trims highly visited branches from the search and focuses the search on rarely occurring branches and paths. This approach gives a significant performance boost while maintaining a high level of coverage. Experimental results show that BEACON is able to achieve very high branch coverages with a fraction of computational cost. In addition, previous hard-to-reach corner states in the ITC99 benchmarks have now been reached by BEACON. New states can also be discovered from the RTL descriptions. For many circuits, one to two orders of magnitude speedups over existing methods have been achieved.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125477537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Calibration of a flexible high precision Power-On Reset during production test","authors":"G. Hilber, D. Gruber, M. Sams, T. Ostermann","doi":"10.1109/TEST.2012.6401562","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401562","url":null,"abstract":"This paper describes a Power-On Reset (POR) circuit with very accurate threshold voltage levels. These voltage levels are achieved by calibrating an on-chip programmable voltage reference during the wafer sort or final test. Two different calibration methods are proposed. One which calibrates the reference voltage of a comparator and another method which calibrates the POR threshold voltage levels itself. Not only the variation of the POR threshold voltage levels can be reduced from 90mV to 7mV, but also the absolute value can be changed.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127984054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Ding, M. Pan, W. Wong, Daniel Chow, Mike P. Li, Sergey Shumarayev
{"title":"On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing","authors":"W. Ding, M. Pan, W. Wong, Daniel Chow, Mike P. Li, Sergey Shumarayev","doi":"10.1109/TEST.2012.6401536","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401536","url":null,"abstract":"Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations and layout dependent effects. On-die instrumentation (ODI) is an effective means to alleviate many of the challenges, as well as characterize and margin performance. This paper covers two of the ODI techniques used in the design of a wide range 28nm, 28Gbps transceiver.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122223918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation","authors":"Yuta Yamato, T. Yoneda, K. Hatayama, M. Inoue","doi":"10.1109/TEST.2012.6401549","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401549","url":null,"abstract":"In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}