2012 IEEE International Test Conference最新文献

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Improving test compression by retaining non-pivot free variables in sequential linear decompressors 通过在顺序线性减压器中保留非枢轴自由变量来改进测试压缩
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401557
Sreenivaas S. Muthyala, N. Touba
{"title":"Improving test compression by retaining non-pivot free variables in sequential linear decompressors","authors":"Sreenivaas S. Muthyala, N. Touba","doi":"10.1109/TEST.2012.6401557","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401557","url":null,"abstract":"Sequential linear decompressors are inherently efficient and attractive for compressing test cubes with many don't cares. The test cubes are encoded by solving a system of linear equations. In continuous decompression, typically a fixed number of free variables are used to encode each test cube in a “one-size-fits-all” manner. The non-pivot free variables used in Gaussian elimination are wasted when the decompressor is reset before decompressing the next test cube. This paper explores techniques for retaining the non-pivot free variables for a test cube and using them to help encode subsequent test cubes and hence improve encoding efficiency. This approach retains most of the non-pivot free variables with only a minimal increase in runtime for solving the equations and no added control information. Experimental results are presented showing that the encoding efficiency, and hence compression, can be significantly boosted.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116528514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Testing strategies for a 9T sub-threshold SRAM 9T亚阈值SRAM的测试策略
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401577
Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, M. Chao, Ming-Hsien Tu, S. Jou, C. Chuang
{"title":"Testing strategies for a 9T sub-threshold SRAM","authors":"Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, M. Chao, Ming-Hsien Tu, S. Jou, C. Chuang","doi":"10.1109/TEST.2012.6401577","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401577","url":null,"abstract":"Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127659146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability 8Gbps CMOS引脚电子硬件宏,具有同步双向能力
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401543
S. Kojima, Y. Arai, Tasuku Fujibe, T. Ataka, A. Ono, Ken-ichi Sawada, D. Watanabe
{"title":"8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability","authors":"S. Kojima, Y. Arai, Tasuku Fujibe, T. Ataka, A. Ono, Ken-ichi Sawada, D. Watanabe","doi":"10.1109/TEST.2012.6401543","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401543","url":null,"abstract":"In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116996136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Systematic defect screening in controlled experiments using volume diagnosis 容积诊断在对照实验中的系统缺陷筛查
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401546
B. Seshadri, P. Gupta, Y. T. Lin, B. Cory
{"title":"Systematic defect screening in controlled experiments using volume diagnosis","authors":"B. Seshadri, P. Gupta, Y. T. Lin, B. Cory","doi":"10.1109/TEST.2012.6401546","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401546","url":null,"abstract":"Controlled modification of different process parameters, using designed experiments, is a key method of achieving high yield in a volume manufacturing environment. However, these changes need to be validated extensively and screened for new systematic defects before release to production. This work presents a novel approach of using volume diagnosis to aid in the screening process. Silicon case studies are presented to validate the production worthiness of this approach.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122980358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Root cause identification of an hard-to-find on-chip power supply coupling fail 难以找到的片上电源耦合故障的根本原因识别
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401563
F. Stellari, T. Cowell, P. Song, M. Sorna, Z. Deniz, J. Bulzacchelli, N. Mitra
{"title":"Root cause identification of an hard-to-find on-chip power supply coupling fail","authors":"F. Stellari, T. Cowell, P. Song, M. Sorna, Z. Deniz, J. Bulzacchelli, N. Mitra","doi":"10.1109/TEST.2012.6401563","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401563","url":null,"abstract":"In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the problem. In addition, we will show how high resolution mapping of the Light Emission from Off-State Leakage Current (LEOSLC) from the chip was instrumental in leading the investigative effort to the right root cause. The problem was successfully traced to a p-FET used for IDDQ measurement during manufacturing test that caused an undesirable coupling path. Fortunately this specific configuration was unique to this particular design and was easy to fix with a single mask change.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131673568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Functional test content optimization for peak-power validation — An experimental study 峰值功率验证的功能测试内容优化-实验研究
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401586
Vinayak Kamath, Wen Chen, N. Sumikawa, Li-C. Wang
{"title":"Functional test content optimization for peak-power validation — An experimental study","authors":"Vinayak Kamath, Wen Chen, N. Sumikawa, Li-C. Wang","doi":"10.1109/TEST.2012.6401586","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401586","url":null,"abstract":"One of the challenges of functional test content optimization, in the context of performance validation, is to predict from a high level model an event of interest observed in either a detailed simulation or in silicon testing. This work uses peak power validation as an example to study the potential of using learning algorithms to uncover the correlations between the different levels of abstraction. Using the OpenSPARC T2 microprocessor as the driving example, we have studied the use of three learning algorithms for building models to explain the events of interest in the output of a power simulation. These models are built based on features extracted from a high-level view of the design. We show that the learned models can be used to select assembly programs that are likely to produce similar interesting events, and also can be used to produce constrained random assembly programs capable of exposing the events of our interest.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks JEDEC宽i /O内存逻辑芯片栈互连测试的DfT体系结构和ATPG
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401569
Sergej Deutsch, B. Keller, V. Chickermane, Subhasish Mukherjee, Navdeep Sood, S. Goel, Ji-Jan Chen, Ashok Mehta, F. Lee, E. Marinissen
{"title":"DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks","authors":"Sergej Deutsch, B. Keller, V. Chickermane, Subhasish Mukherjee, Navdeep Sood, S. Goel, Ji-Jan Chen, Ashok Mehta, F. Lee, E. Marinissen","doi":"10.1109/TEST.2012.6401569","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401569","url":null,"abstract":"Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130651722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Functional test of small-delay faults using SAT and Craig interpolation 基于SAT和Craig插值的小延迟故障功能测试
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401550
M. Sauer, Stefan Kupferschmid, A. Czutro, I. Polian, S. Reddy, B. Becker
{"title":"Functional test of small-delay faults using SAT and Craig interpolation","authors":"M. Sauer, Stefan Kupferschmid, A. Czutro, I. Polian, S. Reddy, B. Becker","doi":"10.1109/TEST.2012.6401550","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401550","url":null,"abstract":"We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-checking techniques, SATSEQ provides detection of small-delay faults through the longest functional paths. All test sequences start at the circuit's initial state; therefore, overtesting is avoided. Moreover, potential invalidation of the fault detection is taken into account. Experimental results show high detection and better performance than scan testing in terms of test application time and overtesting-avoidance.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121213214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization 基于非相干欠采样和后端成本优化的低成本宽带周期信号重构
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401552
Nicholas Tzou, D. Bhatta, S. Hsiao, H. Choi, A. Chatterjee
{"title":"Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization","authors":"Nicholas Tzou, D. Bhatta, S. Hsiao, H. Choi, A. Chatterjee","doi":"10.1109/TEST.2012.6401552","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401552","url":null,"abstract":"Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock synchronization and ADC speed issues) to design a low cost instrumentation for high speed signal capture. A novel signal reconstruction algorithm is developed along with a method for calibrating the effects of unknown delays in data acquisition hardware due to mismatch in signal path lengths on the reconstructed signal. Simulation results and preliminary hardware validation prove the feasibility of the proposed technique.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116441515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Cell-aware Production test results from a 32-nm notebook processor 32nm笔记本处理器的生产测试结果
2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401533
F. Hapke, Michael Reese, J. Rivers, A. Over, V. Ravikumar, W. Redemund, Andreas Glowatz, J. Schlöffel, J. Rajski
{"title":"Cell-aware Production test results from a 32-nm notebook processor","authors":"F. Hapke, Michael Reese, J. Rivers, A. Over, V. Ravikumar, W. Redemund, Andreas Glowatz, J. Schlöffel, J. Rajski","doi":"10.1109/TEST.2012.6401533","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401533","url":null,"abstract":"This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126630875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
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