Root cause identification of an hard-to-find on-chip power supply coupling fail

F. Stellari, T. Cowell, P. Song, M. Sorna, Z. Deniz, J. Bulzacchelli, N. Mitra
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引用次数: 2

Abstract

In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the problem. In addition, we will show how high resolution mapping of the Light Emission from Off-State Leakage Current (LEOSLC) from the chip was instrumental in leading the investigative effort to the right root cause. The problem was successfully traced to a p-FET used for IDDQ measurement during manufacturing test that caused an undesirable coupling path. Fortunately this specific configuration was unique to this particular design and was easy to fix with a single mask change.
难以找到的片上电源耦合故障的根本原因识别
在本文中,我们将介绍一个难以发现的故障条件的诊断测试案例,该故障条件导致IBM 65nm批量技术制造的芯片意外部分上电。特别是,我们将描述故障条件以及电气测试、光学方法和详细电路分析的结合使用,这些方法用于成功地确定问题的根本原因。此外,我们将展示如何高分辨率映射的光发射从状态泄漏电流(LEOSLC)从芯片是如何引导调查工作的正确的根本原因。问题成功地追溯到制造测试中用于IDDQ测量的p-FET,导致了不良的耦合路径。幸运的是,这种特定的配置对于这种特定的设计是独一无二的,并且很容易通过单个掩码更改来修复。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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