8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability

S. Kojima, Y. Arai, Tasuku Fujibe, T. Ataka, A. Ono, Ken-ichi Sawada, D. Watanabe
{"title":"8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability","authors":"S. Kojima, Y. Arai, Tasuku Fujibe, T. Ataka, A. Ono, Ken-ichi Sawada, D. Watanabe","doi":"10.1109/TEST.2012.6401543","DOIUrl":null,"url":null,"abstract":"In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2012.6401543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system.
8Gbps CMOS引脚电子硬件宏,具有同步双向能力
在本文中,我们提出了一个适用于8Gbps实时功能测试的小型CMOS引脚电子硬件宏。宏包括一个驱动器、比较器、dac和控制逻辑嵌入在一个面积为2mm × 1.6mm的区域内。由于宏是在65nm标准CMOS工艺上实现的,它可以与模式生成器和时序生成器一起实现,以实现单芯片引脚电子解决方案。此外,宏能够同时进行双向(SBD)信令,大大缩短了测试时间。讨论了一种简单可靠的SBD评价方法。我们已经将我们的宏应用到测试芯片上,以证明宏适用于8Gbps的测试系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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