2012 IEEE International Test Conference最新文献_第4页

A digital method for phase noise measurement 相位噪声的数字测量方法

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401537

A. Ecker, Kenneth Blakkan, M. Soma

引用次数: 16

Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors 现代微处理器中基于漏洞的多比特扰流(MBU)保护交织

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401594

M. Maniatakos, M. Michael, Y. Makris

{"title":"Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors","authors":"M. Maniatakos, M. Michael, Y. Makris","doi":"10.1109/TEST.2012.6401594","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401594","url":null,"abstract":"We present a novel methodology for protecting incore microprocessor memory arrays from Multiple Bit Upsets (MBUs). Recent radiation studies in modern SRAMs demonstrate that up to 55% of Single Event Upsets (SEUs) due to alpha particle or neutron strikes result in MBUs. Towards suppressing these MBUs, methods such as physical interleaving or periodic scrubbing have been successfully applied to caches. However, these methods are not applicable to in-core, high-performance Content-Addressable Memories (CAM) arrays, due to computational complexity, high delay and area overhead, and lack of information redundancy. To this end, we propose a cost-effective method for enhancing in-core memory array resiliency, called Vulnerability-based Interleaving (VBI). VBI physically disperses bit-lines based on their vulnerability factor and applies selective parity to these lines. Thereby, VBI aims to ensure that an MBU will affect at most one critical bit-field, so that the selective parity will detect the error and a subsequent pipeline flush will remove its effects. Experimental results employing simulation of realistic MBU fault models on the instruction queue of the Alpha 21264 microprocessor in a 65nm process, demonstrate that a 30% selective parity protection of VBI-arranged bit-lines reduces vulnerability by 94%.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134020959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling 低成本高速测试数据采集:使用非相干子采样的精确周期估计驱动信号重构

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401591

Thomas Moon, H. Choi, A. Chatterjee

引用次数: 3

Packet-based JTAG for remote testing 用于远程测试的基于数据包的JTAG

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401573

M. Portolan

引用次数: 2

Event-driven framework for configurable runtime system observability for SOC designs 用于SOC设计的可配置运行时系统可观察性的事件驱动框架

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401554

Jong Chul Lee, Faycel Kouteib, Roman L. Lysecky

引用次数: 2

Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking 径向缺陷聚类对晶圆间3D堆叠IC成品率的影响

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401567

Eshan Singh

{"title":"Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking","authors":"Eshan Singh","doi":"10.1109/TEST.2012.6401567","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401567","url":null,"abstract":"We present and evaluate a simulation methodology to model the impact of the radial clustering of defects on wafers on the yield of 3D ICs manufactured using wafer to wafer stacking. Our simulations draw on an extensively validated model for radial yield degradation on wafers from the literature to incorporate the effect of this key contributor to the widely observed clustering of defects on semiconductor wafers. Current 3D-SIC yield estimation methods ignore defect clustering and assume a uniform distribution of defective dies on each wafer. Our results show that the radial clustering of defective dies causes stacked die yields to be significantly higher than that projected by current models. For 4-5 layer stacks the difference can be 50% or more. Our simulation studies are further validated by comparison with actual silicon data, which suggests that even the more accurate yield estimates from our improved methodology may be somewhat pessimistic. Thus the results presented here show that in practice degradation in stacked die yield from compounding may not be as severe as commonly estimated. This has significant implications in evaluating cost trade-offs associated with 3D-SIC manufacturing.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114271187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter 多千兆赫任意时序发生器和数据模式序列化/格式化器

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401544

D. Keezer, Te-Hui Chen, C. Gray, H. Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo

引用次数: 3

DART: Dependable VLSI test architecture and its implementation DART:可靠的VLSI测试架构及其实现

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401581

Yasuo Sato, S. Kajihara, T. Yoneda, K. Hatayama, M. Inoue, Y. Miura, Satosni Untake, T. Hasegawa, Motoyuki Sato, K. Shimamura

引用次数: 22

Power integrity control of ATE for emulating power supply fluctuations on customer environment 仿真客户环境下电源波动的ATE电源完整性控制

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401553

M. Ishida, T. Nakura, T. Kikkawa, Takashi Kusaka, S. Komatsu, K. Asada

引用次数: 7

Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters 采用时间交错混合模式数据转换器合成高于奈奎斯特测试波形并注入数字相位噪声

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401538

Xian Wang, H. Choi, Thomas Moon, Nicholas Tzou, A. Chatterjee

引用次数: 8