Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction

Abstract

This paper introduces new capability on System on a Chip (SoC) ATE, called "Functional Test Abstraction (FTA)", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.