{"title":"利用功能测试抽象在EDA上自动生成系统级功能测试程序","authors":"Motoo Ueda, Shinichi Ishikawa, Masaru Goishi, Satoru Kitagawa, Hiroshi Araki, Shuichi Inage","doi":"10.1109/TEST.2012.6401590","DOIUrl":null,"url":null,"abstract":"This paper introduces new capability on System on a Chip (SoC) ATE, called \"Functional Test Abstraction (FTA)\", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction\",\"authors\":\"Motoo Ueda, Shinichi Ishikawa, Masaru Goishi, Satoru Kitagawa, Hiroshi Araki, Shuichi Inage\",\"doi\":\"10.1109/TEST.2012.6401590\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces new capability on System on a Chip (SoC) ATE, called \\\"Functional Test Abstraction (FTA)\\\", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.\",\"PeriodicalId\":353290,\"journal\":{\"name\":\"2012 IEEE International Test Conference\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2012.6401590\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2012.6401590","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction
This paper introduces new capability on System on a Chip (SoC) ATE, called "Functional Test Abstraction (FTA)", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces of the same or different types.