Capacitive sensing testability in complex memory devices

Abstract

Printed circuit boards (PCB) with soldered-down arrays of advanced memory devices are growing more common and present a class of difficult testing problems to PCB manufacturing. With the large memory capacities now available, memory expansion connectors are less necessary, and many products have reduced form factors (thinness) that means upright memory DIMM arrays are being phased out. When memory devices are soldered down, they become part of the board test problem, where in the past it was only necessary to test the empty sockets that would later be populated with memory. This paper discusses a Design-for-Test (DFT) technology that can be easily applied to memory devices which is independent of the silicon, and only impacts the design of the package the memory is placed within. This means DFT can be retrofitted to memories already in production without a costly silicon design change.