2012 IEEE International Test Conference最新文献_第6页

RNA: Advanced phase tracking method for digital waveform reconstruction RNA:用于数字波形重建的高级相位跟踪方法

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401592

Takashi Ito, H. Okawara, Jinlei Liu

{"title":"RNA: Advanced phase tracking method for digital waveform reconstruction","authors":"Takashi Ito, H. Okawara, Jinlei Liu","doi":"10.1109/TEST.2012.6401592","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401592","url":null,"abstract":"This paper describes how to measure an eye diagram by using ATE (Automated Test Equipment) digital channel and to do a correlation with an oscilloscope for over-Giga-bps class high speed digital interfaces. The novel method named RNA (Recovering aNAlysis) is a post processing method to perform “phase tracking” in the eye diagram measurement on an ATE which does not have a CDR (Clock Data Recovery) hardware integrated. The RNA is an enhancement of the method named DNA (Data aNAlysis) that constructs an eye diagram by coherent waveform reconstruction with utilizing an ATE digital channel. The DNA is an elegant method to reconstruct digital signal waveform and its eye diagram; however it is not immune to slow jitter or wander of signal. In recent high speed digital interfaces, jitter tolerance is very critical so that the DNA is insufficient for coping with test devices containing slow jitter. The RNA is an enhanced DNA by implementing software quasi-CDR described in this paper. It significantly expands the application coverage. The eye diagram processed by this method is improved and good for parametric measurement such as rise time/fall time tests. Especially, it allows to do an easy correlation to the eye measured by an oscilloscope. Therefore the transition from bench systems to ATE for production test becomes smooth and efficient.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126468028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Scan test of die logic in 3D ICs using TSV probing 三维集成电路中使用TSV探针的芯片逻辑扫描测试

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401568

Brandon Noia, Shreepad Panth, K. Chakrabarty, S. Lim

{"title":"Scan test of die logic in 3D ICs using TSV probing","authors":"Brandon Noia, Shreepad Panth, K. Chakrabarty, S. Lim","doi":"10.1109/TEST.2012.6401568","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401568","url":null,"abstract":"Pre-bond testing of TSVs and die logic is a significant challenge and a potential roadblock for 3D integration. BIST solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide pre-bond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and pre-bond scan test. Two possible pre-bond scan test configurations are shown - they provide varying degrees of test parallelism. HSPICE simulations are performed on a logic-on-logic 3D benchmark. Results show that the ratio of the number of probe needles available for test access to the number of pre-bond scan chains determines which pre-bond scan configuration results in the shortest test time. Maximum pre-bond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3D design. These clock speeds show that pre-bond scan test can be performed quickly, at a speed that is comparable to scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during pre-bond scan test. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.2% for three dies in the 3D stack.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"34 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132056718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Low power programmable PRPG with enhanced fault coverage gradient 具有增强故障覆盖梯度的低功耗可编程PRPG

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401559

J. Solecki, J. Tyszer, Grzegorz Mrugalski, N. Mukherjee, J. Rajski

引用次数: 8

In-system constrained-random stimuli generation for post-silicon validation 后硅验证的系统内约束随机刺激生成

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401541

A. Kinsman, Ho Fai Ko, N. Nicolici

引用次数: 11

FPGA-based synthetic instrumentation for board test 基于fpga的电路板综合测试仪器

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401571

I. Aleksejev, A. Jutman, S. Devadze, S. Odintsov, T. Wenzel

引用次数: 22

An ATE architecture for implementing very high efficiency concurrent testing 用于实现非常高效的并发测试的ATE体系结构

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401551

Takahiro Nakajima, Takeshi Yaguchi, Hajime Sugimura

引用次数: 7

Experiences with non-intrusive sensors for RF built-in test 具有射频内置测试非侵入式传感器的经验

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401587

L. Abdallah, H. Stratigopoulos, S. Mir, C. Kelma

引用次数: 30

An experiment of burn-in time reduction based on parametric test analysis 基于参数测试分析的减耗时间试验

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401595

N. Sumikawa, Li-C. Wang, M. Abadir

引用次数: 34

Improved volume diagnosis throughput using dynamic design partitioning 使用动态设计分区改进卷诊断吞吐量

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401564

Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, S. Reddy, B. Benware

{"title":"Improved volume diagnosis throughput using dynamic design partitioning","authors":"Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, S. Reddy, B. Benware","doi":"10.1109/TEST.2012.6401564","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401564","url":null,"abstract":"A method based on dynamic design partition is presented to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time T using given constrained computational resources C. Recently we proposed a static design partitioning method to reduce the diagnosis memory footprint for large designs [1] to achieve this objective. The method in [1] is applied once for each design without using the information of test patterns and failure files, and then diagnosis is performed on an appropriate block(s) of the design partition for a failure file. Even though the memory footprint of diagnosis is reduced the diagnosis quality is impacted to unacceptable levels for some types of defects such as bridges. In this paper, we propose a new failure dependent design partitioning method to improve volume diagnosis throughput with a minimal impact on diagnosis quality. For each failure file, the proposed method first determines the small partition needed to diagnose this failure, and then performs the diagnosis on this partition instead of the complete design. Since the partition is far smaller, both the run time and the memory usage of diagnosis can be significantly reduced better than when earlier proposed static partition is used. Extensive experiments were conducted on several large industrial designs to validate the proposed method. It has been observed that the typical partition size for various defects is less than 3% of the size of the original design. Also diagnosis runs much faster (>;2X) on the partition. Combining these two factors, the throughput of volume diagnosis can be improved by an order of magnitude.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

A design flow to maximize yield/area of physical devices via redundancy 通过冗余来最大化物理设备的产量/面积的设计流程

2012 IEEE International Test Conference Pub Date : 2012-11-05 DOI: 10.1109/TEST.2012.6401582

M. Mirza-Aghatabar, M. Breuer, S. Gupta

{"title":"A design flow to maximize yield/area of physical devices via redundancy","authors":"M. Mirza-Aghatabar, M. Breuer, S. Gupta","doi":"10.1109/TEST.2012.6401582","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401582","url":null,"abstract":"This paper deals with using redundancy to maximize the number of “workable” die one can produce from a silicon wafer. When redundant modules are used to enhance yield, several issues need to be addressed, such as power, performance degradation, testability, area, and partitioning the original logic design into modules. The focus of this paper is on the long ignored issue of partitioning and clustering to form modules that are to be replicated. For this purpose we propose a design flow with two phases. The first phase consists of a partitioning process that generates all combinational logic blocks (CLBs) of a given logic circuit. CLB partitioning addresses design and test constraints such as timing closure and testing complexity, by using redundancy at finer levels of granularity. In the second phase we carry out an overall optimization of the generated CLBs to find the optimal level of granularity for replication to maximize yield/area. Using a real design (OpenSPARC T2) and defect densities projected in the near future, the experimental results show that the output of our design flow outperforms the traditional redundant design with spare core, e.g. we achieved 1.1 to 13.3 times better yield/area as a function of defect density.","PeriodicalId":353290,"journal":{"name":"2012 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125619120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2