A design flow to maximize yield/area of physical devices via redundancy

This paper deals with using redundancy to maximize the number of “workable” die one can produce from a silicon wafer. When redundant modules are used to enhance yield, several issues need to be addressed, such as power, performance degradation, testability, area, and partitioning the original logic design into modules. The focus of this paper is on the long ignored issue of partitioning and clustering to form modules that are to be replicated. For this purpose we propose a design flow with two phases. The first phase consists of a partitioning process that generates all combinational logic blocks (CLBs) of a given logic circuit. CLB partitioning addresses design and test constraints such as timing closure and testing complexity, by using redundancy at finer levels of granularity. In the second phase we carry out an overall optimization of the generated CLBs to find the optimal level of granularity for replication to maximize yield/area. Using a real design (OpenSPARC T2) and defect densities projected in the near future, the experimental results show that the output of our design flow outperforms the traditional redundant design with spare core, e.g. we achieved 1.1 to 13.3 times better yield/area as a function of defect density.