Scan test of die logic in 3D ICs using TSV probing

Abstract

Pre-bond testing of TSVs and die logic is a significant challenge and a potential roadblock for 3D integration. BIST solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide pre-bond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and pre-bond scan test. Two possible pre-bond scan test configurations are shown - they provide varying degrees of test parallelism. HSPICE simulations are performed on a logic-on-logic 3D benchmark. Results show that the ratio of the number of probe needles available for test access to the number of pre-bond scan chains determines which pre-bond scan configuration results in the shortest test time. Maximum pre-bond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3D design. These clock speeds show that pre-bond scan test can be performed quickly, at a speed that is comparable to scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during pre-bond scan test. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.2% for three dies in the 3D stack.