Board assisted-BIST: Long and short term solutions for testpoint erosion — Reaching into the DFx toolbox

Abstract

Testpoint erosion, the continuously increasing loss of physical net/node access at the In-Circuit Test process step is putting board test strategies at risk [1]. In response, the International Electronics Manufacturing Industry (iNEMI) [2] 2009 road map and gap analysis [3] efforts launched a Technology Integration Group (TIG) `Built-in Self-Test Project' or `BIST projecty' [4] to drive a new test strategy. Integrated Circuit (IC) BIST was identified as a solution and the electronics industry was surveyed to ratify the decision. After analysis of the survey, the TIG determined that a two-tier strategy was needed. This paper presents key survey findings and the two tier strategies for both the long and short term to identify standardization requirements for IC BIST usage at the board-level.