{"title":"Nonequilibrium nondissipative thermodynamics - and its application to diamond film deposition","authors":"Jitao Wang","doi":"10.1109/ICSICT.2001.982170","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982170","url":null,"abstract":"The equality of the 2/sup nd/ law of thermodynamics had been regarded as the sufficient and necessary condition for a system being in equilibrium for about 150 years. However, such a classical or traditional basic concept should be overthrown or changed for complex systems including nonspontaneous reaction(s). Therefore, a new field of nonequilibrium nondissipative thermodynamics has been introduced by the author into a complete systematization of modem thermodynamics. Nonequilibrium nondissipative thermodynamics provides a solid theoretical base for quantitative calculation of nonequilibrium phase diagrams. A series of calculated nonequilibrium phase diagrams for activated low pressure diamond films deposition agree excellently with a great number of experimental data reported in the literature. Nonequilibrium nondissipative thermodynamics and the nonequilibrium phase diagram theorem can also be used for cubic boron nitride deposition and other solid-state and integrated circuit technology.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123532405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The development of the nanocrystal silicon film FEA pressure sensor","authors":"L. Jinhua, Lin Hongyi, Zhang Xing","doi":"10.1109/ICSICT.2001.982014","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982014","url":null,"abstract":"A novel field emission array (FEA) has been fabricated using a new method, which greatly simplifies the whole process. Factors influencing the emitting current of the FEA are analyzed theoretically and nanocrystal silicon films are deposited on the FEA to improve the emitting characteristics due to their excellent conductivity and particular configuration. Emitting characteristics of the FEA with and without nanocrystal silicon films are tested and compared. The design and the main process are proposed.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123584473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"30 nm device channel profile optimization for digital application by using numerical simulation","authors":"Gongchuan Li, Wenli Wang, L. Qi, K. Joardar","doi":"10.1109/ICSICT.2001.982035","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982035","url":null,"abstract":"Bulk and novel MOSFET structures with gatelengths in 30 nm regime are expected to become industry standards in approximately 2007. In this article we discuss the application of TCAD to the study of analytical (idealized) MOSFET structures in this regime. The electrical properties of 30 nm planar NMOSFET with super halo structure were described with the help of semi-classical transport simulation. in ISE-DESSIS. The device was optimized through an advanced process and device synthesis system, the 3.13e -4 A//spl mu/m saturation current and 8.0e -11 A//spl mu/m leakage current at supply voltage Vd = 0.6 V were obtained for low power and high performance application.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123592832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinfeng Kang, Xiaoyan Liu, R. Han, Yangyuan Wang, G. Lian, K. Xun, D. Yu, G. Xiong, S.C. Wu, Y. Wang
{"title":"Structural and electrical properties of CeO/sub 2//Si with nitrided interfacial layer by nitrogen ion beam bombardment","authors":"Jinfeng Kang, Xiaoyan Liu, R. Han, Yangyuan Wang, G. Lian, K. Xun, D. Yu, G. Xiong, S.C. Wu, Y. Wang","doi":"10.1109/ICSICT.2001.981485","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981485","url":null,"abstract":"The effects of nitrided interfacial layer between CeO/sub 2/-Si on the interfacial properties are studied. The process of nitrogen ion beam bombardment (NIBB) was used to form the nitride dielectric-Si interface. The CeO/sub 2/ high-k dielectric films were grown on Si[100] substrates by pulsed laser deposition (PLD) and the capacitors with Pt/CeO/sub 2//Si structure were fabricated. The atomic force microscopy (AFM), x-ray photoelectron spectroscopy (XPS), high-resolution transmission electron microscopy (HRTEM), capacitance-voltage (C-V), and current-voltage (I-V) methods were used to study the interfacial characteristics of the samples. The results showed that a SiN/sub x/O/sub y/ layer was formed on Si surface by the NIBB process. The nitride layer between CeO/sub 2/ and Si can suppress the further formation of interfacial layer between CeO/sub 2/ and Si, which is helpful to improve the structural and electrical characteristics of CeO/sub 2/-Si interface.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced chemical mechanical planarization (CMP) process for copper interconnects","authors":"T. Hara","doi":"10.1109/ICSICT.2001.981501","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981501","url":null,"abstract":"Chemical mechanical planarization (CMP) of copper dual Damascene is described. Dishing of the copper layer can be controlled by the CMP employing non-abrasive MnO/sub 2/ slurry. Removal rate ratio of the Cu/barrier layer can be reduced from 2.8 to unity with doping of antioxide additive in the slurry. Dishing still appears at the rate of 2.8 and dishing free CMP can be attained at unit. Scratches are formed in this CMP.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126186376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wei Ke, Liu Xun-chun, Guo Xiao-xu, Wang Run-mei, Cao Zhen-Ya
{"title":"ICP dry etching for deep sub-micrometer vertical trench in Si and SiO/sub 2/","authors":"Wei Ke, Liu Xun-chun, Guo Xiao-xu, Wang Run-mei, Cao Zhen-Ya","doi":"10.1109/ICSICT.2001.981516","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981516","url":null,"abstract":"Dry etching is a very important process in integrated circuit manufacture. Perfect results of etching a 154 nm trench in silicon and a 138 nm trench in silicon dioxide by a pagoda-shape ICP reactor are reported. A detail study of etching characteristics as function of gas composition, flow rate, RF power, pressure and self-bias voltage, is described.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yong-Zhao Han, Yingyu Qu, Yu-Long Jiang, Bei Xu, Yong-Feng Cao, G. Ru, Bingzong Li, P. K. Chu
{"title":"Ni(Pt)Si thin film formation and its electrical characteristics with Si substrate","authors":"Yong-Zhao Han, Yingyu Qu, Yu-Long Jiang, Bei Xu, Yong-Feng Cao, G. Ru, Bingzong Li, P. K. Chu","doi":"10.1109/ICSICT.2001.981530","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981530","url":null,"abstract":"The solid phase silicidations for the bilayers of Ni/Pt and Pt/Ni sputtered on Si[100] substrates were studied. The effect of Pt addition in the NiSi film on its thermal stability enhancement was investigated. The results show that the phase transformation from Ni(Pt)Si to NiSi/sub 2/ was delayed to higher temperature than the Ni/Si system without Pt as a capping- or inter-layer by more than 100/spl deg/C. The apparent Schottky barrier height of Ni(Pt)Si/n-Si(111) is modulated with the Pt content, and the electrical characteristic is good in the silicidation temperature of 500-800/spl deg/C.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High speed LIGBT with localized lifetime control by using high dose and low energy helium implantation","authors":"Jian Fang, Zhaoji Li, Hongyan Li, Jian Yang","doi":"10.1109/ICSICT.2001.981448","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981448","url":null,"abstract":"A high speed LIGBT with localized lifetime control by using high dose and low energy helium implantation (LC-IGBT) is proposed. Compared with AS-LIGBTs and the conventional LIGBTs, the partial irradiation results show that trade-off relationship between turn-off time and forward voltage drop has been improved. It is the advanced lifetime control method stable for huge thermal budget and applicable in any steps of device fabrication, so that it improves lifetime engineering possibilities in power integrated circuit with respected to conventional lifetime control methods.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kailiang Zhang, Yu-ling Liu, Fang Wang, Tian-Lei Si
{"title":"Study on controlling the adsorption state of particle on the polished silicon wafer","authors":"Kailiang Zhang, Yu-ling Liu, Fang Wang, Tian-Lei Si","doi":"10.1109/ICSICT.2001.981518","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981518","url":null,"abstract":"With the feature size of ULSI becoming smaller and smaller, the surface quality of the polished silicon wafer becomes more and more important. In this paper, the adsorption state of a particle on the polished silicon wafer and the preferential adsorption model are studied, on the basis of which the non-ion surfactant is chosen as the second kind of adsorbate, which is preferentially adsorbed onto the polished silicon wafer and is easily washed out. Experiment results show that the application of the surfactant makes the adsorbate keep in physical adsorption that is easy to wash out for 120 h, but it may be kept in physical adsorption for 2 h by using the common washing method. The method in this paper has many advantages such as lower cost, higher efficiency and easily operation and so on. What's more, it is also apt to produce large scale circuits.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weiguo Di, Yu-ling Liu, B. Tan, Weiwei Li, Ming Yang
{"title":"The research of silicon wafer's polishing fog","authors":"Weiguo Di, Yu-ling Liu, B. Tan, Weiwei Li, Ming Yang","doi":"10.1109/ICSICT.2001.981477","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981477","url":null,"abstract":"In this paper, the mechanism of producing polishing fog is studied. The factors that influence polishing fog are analysis. Optimizing polishing technology on the basis of experiments can control the polishing fog.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130703334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}