30 nm device channel profile optimization for digital application by using numerical simulation

Abstract

Bulk and novel MOSFET structures with gatelengths in 30 nm regime are expected to become industry standards in approximately 2007. In this article we discuss the application of TCAD to the study of analytical (idealized) MOSFET structures in this regime. The electrical properties of 30 nm planar NMOSFET with super halo structure were described with the help of semi-classical transport simulation. in ISE-DESSIS. The device was optimized through an advanced process and device synthesis system, the 3.13e -4 A//spl mu/m saturation current and 8.0e -11 A//spl mu/m leakage current at supply voltage Vd = 0.6 V were obtained for low power and high performance application.