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2011 International Symposium on Electronic System Design最新文献

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Design and Implementation of Low Power Smart PV Energy System for Portable Applications Using Synchronous Buck Converter 基于同步降压变换器的便携式低功耗智能光伏能源系统的设计与实现
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.56
B. Babu, Sriharsha, M. Kumar, Nikhil Saroagi, S. Samantaray
{"title":"Design and Implementation of Low Power Smart PV Energy System for Portable Applications Using Synchronous Buck Converter","authors":"B. Babu, Sriharsha, M. Kumar, Nikhil Saroagi, S. Samantaray","doi":"10.1109/ISED.2011.56","DOIUrl":"https://doi.org/10.1109/ISED.2011.56","url":null,"abstract":"In this paper, synchronous buck converter based PV energy system for portable applications, especially low power device applications such as charging mobile phone batteries are considered. The converter topology used here is soft switching technique to reduce the switching losses which is found prominently in the conventional buck converter, thus efficiency of the system is improved and the heating of MOSFETs due to switching losses reduce and the MOSFETs have a longer life. The dc power extracted from the PV array is synthesized and modulated by the converter to suit the load requirements. Further, a charging method is studied with controller to regulate the battery voltage and current without overheating. As a result, the charging efficiency can be improved by soft switching technique. Besides, the performance is obtained less number of components and the developed system is cost effective and highly portable. The proposed system is simulated in the MATLAB-Simulink environment and the practical implementation of the proposed converter is done to validate the theoretical results.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126843457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Low Complexity Flexible Hardware Efficient Decimation Selector 低复杂性灵活的硬件高效抽取选择器
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.18
V. Rakesh, K. G. Smitha, A. P. Vinod
{"title":"Low Complexity Flexible Hardware Efficient Decimation Selector","authors":"V. Rakesh, K. G. Smitha, A. P. Vinod","doi":"10.1109/ISED.2011.18","DOIUrl":"https://doi.org/10.1109/ISED.2011.18","url":null,"abstract":"Coefficient decimation (CD) is a computationally efficient reconfigurable finite impulse response (FIR) filter method. Reconfigurability is achieved by decimating the fixed coefficient modal (prototype) filter in-order to realize variable bandwidth responses. Reconfigurable decimation selector is a vital part of the CD architecture which allows the user to select different decimation factor of choice. In this paper, we propose a low complexity, efficient hardware architecture for reconfigurable decimation selector. The implementation results in Virtex IV-xc4vsx35-10ff668 FPGA shows that when compared to other decimation selector techniques available in literature, the proposed implementation technique saves up to 5.2% of area and 7.6% of power for a filter order of 101.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126583972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage 延迟可测试增强扫描触发器:DFT高故障覆盖率
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.25
A. Suhag, V. Shrivastava
{"title":"Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage","authors":"A. Suhag, V. Shrivastava","doi":"10.1109/ISED.2011.25","DOIUrl":"https://doi.org/10.1109/ISED.2011.25","url":null,"abstract":"The Scan based testing is used for delay testing in sequential circuits and in general it is implemented by using launch-on-capture (LoC) delay tests. Launch-on-shift (LoS) delay tests are usually more efficient to obtain high fault coverage with appreciably lesser number of test vectors, but it requires a fast scan enable, which is not supported by majority of designs. The architecture of scan design limits the two pattern delay tests that can be applied to circuit under test which results in degradation of delay test coverage. The use of enhanced scan flip-flops can improve this problem by facilitating arbitrary delay test vector pairs, at the cost of high area overhead and also requires fast hold signal. This paper presents a new enhanced scan methodology implemented with the slow hold signal. Experimental results on ISCAS'89 benchmark circuit shows improvement in TDF fault coverage for this methodology.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122271709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Nonlinear Inductance Measurement Using an Energy Storage Approach 基于储能方法的非线性电感测量
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.72
M. Meena, R. Khanna, Dipankar
{"title":"Nonlinear Inductance Measurement Using an Energy Storage Approach","authors":"M. Meena, R. Khanna, Dipankar","doi":"10.1109/ISED.2011.72","DOIUrl":"https://doi.org/10.1109/ISED.2011.72","url":null,"abstract":"A novel method to measure inductance of power inductors is presented in this paper. Energy stored in inductors was used to measure the nonlinear inductance as function of current flow. Inductance was measured for air core (control sample) and ferrite core inductors with increasing levels of currents through them. It was found that air core inductor behaved linearly as expected. Data for ferrite core inductor provided insight into saturation characteristics of magnetic materials.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132339349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis of Reversible Universal Logic around QCA with Online Testability 具有在线可测试性的QCA可逆通用逻辑的综合
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.53
B. Sen, D. Saran, M. Saha, B. Sikdar
{"title":"Synthesis of Reversible Universal Logic around QCA with Online Testability","authors":"B. Sen, D. Saran, M. Saha, B. Sikdar","doi":"10.1109/ISED.2011.53","DOIUrl":"https://doi.org/10.1109/ISED.2011.53","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the requirement of excessive logic gates as well as its high defect rate limit the performance of a QCA based design. This work proposes a new approach to synthesize the reversible universal QCA logic gate (RUG) with the target to reduce the garbage outputs as well as the number of logic gates to realise a design simultaneously ensuring the defect tolerance. A concurrent error detection methodology is introduced to support the online testing of a circuit designed around the RUG. The experimental designs establish that the RUG can ensure an energy saving cost effective realization of testable QCA circuits.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A Novel Variable Mask Median Filter for Removal of Random Valued Impulses in Digital Images (VMM) 一种用于去除数字图像随机值脉冲的变掩模中值滤波器
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.41
J. K. Mandal, S. Mukhopadhyay
{"title":"A Novel Variable Mask Median Filter for Removal of Random Valued Impulses in Digital Images (VMM)","authors":"J. K. Mandal, S. Mukhopadhyay","doi":"10.1109/ISED.2011.41","DOIUrl":"https://doi.org/10.1109/ISED.2011.41","url":null,"abstract":"This paper presents a novel technique for de noising the images which are corrupted by random valued impulse noise. The detection of noisy pixels is done using variable weights of all neighbor directional pixels through 5 x 5 mask. The proposed operator performs arithmetic absolute differences along with some other arithmetic operations on the pixels aligned in the four main directions with the center pixel to classify test pixel. For filtering we have used an improved median based filtering technique which uses variable mask consisting of nine and twenty five pixels respectively. Certain pixels in the 3 x 3 window are selected prior to compute median operation. Three user supplied parameters are varied in a wide range to obtain the optimal results. The results obtained using the implementation show better de noising capability along with preservation of fine image textures/ details for the images corrupted with random valued impulses.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132460456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter 多带宽10位SAR模数转换器
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.63
M. K. Adimulam, K. K. Movva, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas
{"title":"A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter","authors":"M. K. Adimulam, K. K. Movva, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas","doi":"10.1109/ISED.2011.63","DOIUrl":"https://doi.org/10.1109/ISED.2011.63","url":null,"abstract":"In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"5 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132644925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI Implementation of Wavelet Based Robust Image Watermarking Chip 基于小波鲁棒图像水印芯片的VLSI实现
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.67
T. Lad, A. Darji, S. Merchant, A. Chandorkar
{"title":"VLSI Implementation of Wavelet Based Robust Image Watermarking Chip","authors":"T. Lad, A. Darji, S. Merchant, A. Chandorkar","doi":"10.1109/ISED.2011.67","DOIUrl":"https://doi.org/10.1109/ISED.2011.67","url":null,"abstract":"Progress in the digital multimedia technologies during last decade has offered many facilities in the transmission, reproduction and manipulation of data. However, this advance has also brought the problem such as copyright protection for content providers. Digital watermarking is proposed solution for copy right protection for multimedia. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. The main objective of this paper is to propose very large scale integration (VLSI) architecture for robust and blind image watermarking chip. Watermarking architecture synthesized using Xilinx's ISE for field-programmable gate array (FPGA). For custom integrated chip layout design we use Synopsys's Design Vision and Cadence's SOC Encounter tool. The proposed architecture of watermarking chip requires less area (0.067 mm2), power (3.75 mW) and embedding can be done real time so, it can be integrated in any image acquisition device.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Antenna Considerations for Retail Beamed Power Delivery in India 印度零售波束电力输送的天线考虑
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.66
N. Komerath, A. Kar, R. Pant
{"title":"Antenna Considerations for Retail Beamed Power Delivery in India","authors":"N. Komerath, A. Kar, R. Pant","doi":"10.1109/ISED.2011.66","DOIUrl":"https://doi.org/10.1109/ISED.2011.66","url":null,"abstract":"Past work has shown the relevance of retail electric power delivery in developing areas where the market for micro devices outpaces the power grid infrastructure. Antenna size requirements imply logically that frequencies above 100 GHz must be used for viable power transmission. A power beaming architecture based on near-millimeter waves can enable power exchange at intercontinental, littoral and local levels, enabling participation of micro renewable generators and rural populations. Building on a survey of technological developments, the paper starts the requirements definition for millimeter wave power antenna design. Lighter than air aerostat platforms enable longer horizontal paths to be shifted above the dense, moist lower atmosphere, with vertical transmission between the ground and the aerostat occurring through millimeter wave guides built into tethers. Ground antennae may be integrated with solar photovoltaic panels for multiple uses. The option of transmitting power from local micro generators rather than storing locally, favors the use of technology-intensive mass-produced solid state devices that integrate conversion, transmission, reception and phase variation for beam pointing.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124034829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Authenticated Encryption Based Security Framework for NoC Architectures 基于身份验证加密的NoC体系结构安全框架
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.17
K. Sajeesh, H. Kapoor
{"title":"An Authenticated Encryption Based Security Framework for NoC Architectures","authors":"K. Sajeesh, H. Kapoor","doi":"10.1109/ISED.2011.17","DOIUrl":"https://doi.org/10.1109/ISED.2011.17","url":null,"abstract":"Network on Chip (NoC) is an emerging solution to the existing scalability problems with SoC. However it is exposed to security threats like extraction of secret information from IP cores. In this paper we present an Authenticated Encryption (AE) based security framework for NoC based systems. The security framework resides in Network Interface (NI) of every secure IP core allowing secure communication among such IP cores. We simulated and implemented our framework using Verilog/VHDL modules on top of NoCem emulator. The results showed tolerable area overhead and did not affect the network performance apart from some initial latency.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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