VLSI Implementation of Wavelet Based Robust Image Watermarking Chip

Progress in the digital multimedia technologies during last decade has offered many facilities in the transmission, reproduction and manipulation of data. However, this advance has also brought the problem such as copyright protection for content providers. Digital watermarking is proposed solution for copy right protection for multimedia. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. The main objective of this paper is to propose very large scale integration (VLSI) architecture for robust and blind image watermarking chip. Watermarking architecture synthesized using Xilinx's ISE for field-programmable gate array (FPGA). For custom integrated chip layout design we use Synopsys's Design Vision and Cadence's SOC Encounter tool. The proposed architecture of watermarking chip requires less area (0.067 mm2), power (3.75 mW) and embedding can be done real time so, it can be integrated in any image acquisition device.