M. K. Adimulam, K. K. Movva, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas
{"title":"多带宽10位SAR模数转换器","authors":"M. K. Adimulam, K. K. Movva, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas","doi":"10.1109/ISED.2011.63","DOIUrl":null,"url":null,"abstract":"In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"5 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter\",\"authors\":\"M. K. Adimulam, K. K. Movva, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas\",\"doi\":\"10.1109/ISED.2011.63\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL\",\"PeriodicalId\":349073,\"journal\":{\"name\":\"2011 International Symposium on Electronic System Design\",\"volume\":\"5 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Symposium on Electronic System Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2011.63\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Symposium on Electronic System Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2011.63","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter
In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
