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An Improved BitMask Based Code Compression Algorithm for Embedded Systems 嵌入式系统基于比特掩码的改进代码压缩算法
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.15
W. Wang, C. Lin
{"title":"An Improved BitMask Based Code Compression Algorithm for Embedded Systems","authors":"W. Wang, C. Lin","doi":"10.1109/ISED.2011.15","DOIUrl":"https://doi.org/10.1109/ISED.2011.15","url":null,"abstract":"Engineers must consider performance, power consumption and cost when they design digital systems. Embedded systems are more constrained in all these considerations. Memory is one of the key factors that affect all of them. Code compression is a technique for embedded systems to reduce the memory usage. Bit Mask based code compression is a modified version of dictionary based code compression. The basic of Bit Mask is to record mismatch values and their positions to compress more instructions and use exclusive or operation with the reference instruction to decode the codeword. In this paper, we applied separated dictionary and variable mask numbers to the Bit Mask algorithm to reduce the codeword length of high frequency instructions. A novel dictionary selection algorithm is also proposed to increase the instruction match rates. According to our experimental results, our method can improve in average 3% compression ratio for smaller benchmarks, and over 6% improvement for bigger benchmarks.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127722989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip 基于蚁群优化的数字微流控生物芯片液滴路径技术
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.23
Indrajit Pan, P. Dasgupta, H. Rahaman, T. Samanta
{"title":"Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip","authors":"Indrajit Pan, P. Dasgupta, H. Rahaman, T. Samanta","doi":"10.1109/ISED.2011.23","DOIUrl":"https://doi.org/10.1109/ISED.2011.23","url":null,"abstract":"Digital micro fluidic biochip $(DMFB)$ has gained much importance in recent times, which supports various on chip biological sample analysis. The analysis is performed on a two dimensional micro array. Significant researches are going on for high performance droplet routing in DMFB using computer aided design ($CAD$) techniques. This paper proposes a bio inspired multi objective optimization technique for multiple droplet routing in single source-single destination net (two pin net) and also for dual source - single destination net (three pin net). Our proposed method is based on ant colony optimization $(ACO)$ technique that optimizes the number of electrode usage and routing completion time simultaneously. We run our algorithm on in-vitro, and some other existing benchmarks, and experimental results show improvement in most of the cases.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114216783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A New Look-Up Table Approach for High-Speed Finite Field Multiplication 高速有限域乘法的一种新的查找表方法
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.35
B. K. Meher, P. Meher
{"title":"A New Look-Up Table Approach for High-Speed Finite Field Multiplication","authors":"B. K. Meher, P. Meher","doi":"10.1109/ISED.2011.35","DOIUrl":"https://doi.org/10.1109/ISED.2011.35","url":null,"abstract":"This paper presents a new high-speed multiplier over GF(2^m) based on look-up table (LUT) approach. A straight-forward LUT-based multiplication requires a table of size (m x 2^m) bits for the Galois field of order m which is quite large for the fields of large orders recommended by the National Institute of Standards and Technology (NIST). Therefore, in this paper, we propose a digit-serial LUT-based technique, where certain number of operand bits are grouped into digits, and multiplication is performed in serial/parallel manner. We restrict the digit-size to 4 to store only 16 words in the LUT. We have also proposed a digit-parallel design to achieve higher speed than its digit-serial counterpart, which is very much useful for high-speed applications. We have chosen m=233 to satisfy the security requirements in elliptic curve cryptography, but our method can be used for other prime extensions, as well. We have estimated the area-time complexity of our designs in terms of LUT access-time and XOR-delay. The proposed LUT-based implementation will be useful for high-speed applications in elliptic curve cryptography and error control coding.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"49 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113934099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC Systems 探索集成电路验证方法，用于PLC系统的验证和验证
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.47
M. M. Patil, S. Subbaraman, Shirish Joshi
{"title":"Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC Systems","authors":"M. M. Patil, S. Subbaraman, Shirish Joshi","doi":"10.1109/ISED.2011.47","DOIUrl":"https://doi.org/10.1109/ISED.2011.47","url":null,"abstract":"With increased complexity in control and automation systems, efforts are going on for developing reliable and safe control systems. IEC61131-3 is most commonly used control specification standard. Development of IEC61499 is an effort to utilize proven software engineering practices that can provide benefits such as portability, interoperability, configurability and re-configurability to these systems. But, researchers have raised questions on its effectiveness for defining system level architecture, successful exploitation of current software engineering practices and many other ambiguities [1, 2, and 3]. Irrespective of which standard is used for control specification, verification of such systems and their safety assurance is one of the major challenges.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Cost Software-Implemented Error Detection Technique 低成本软件实现的错误检测技术
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.20
M. Maghsoudloo, H. Zarandi, N. Khoshavi
{"title":"Low-Cost Software-Implemented Error Detection Technique","authors":"M. Maghsoudloo, H. Zarandi, N. Khoshavi","doi":"10.1109/ISED.2011.20","DOIUrl":"https://doi.org/10.1109/ISED.2011.20","url":null,"abstract":"In this paper, a software behavior-based technique is presented to detect control-flow error. The analysis of a key point leads to introduce the proposed technique: effective reduction of the overheads of control-flow checking statements through finding the best sequence of signatures for assigning to consecutive basic-blocks. To evaluate the proposed technique, a functional full-system simulator is used, and several well-known benchmarks are implemented on a quad-core shared memory processor. The experimental results, with regarding to both detection coverage and overheads, demonstrate that on average about 94% of the control-flow errors can be detected by the proposed technique, more efficiently.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126695787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained Devices 资源受限设备的低复杂度说话词识别应用
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.30
G. Dhinesh, G. Jagadeesh, T. Srikanthan
{"title":"A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained Devices","authors":"G. Dhinesh, G. Jagadeesh, T. Srikanthan","doi":"10.1109/ISED.2011.30","DOIUrl":"https://doi.org/10.1109/ISED.2011.30","url":null,"abstract":"We present a low-complexity solution for performing speaker-and-word recognition and demonstrate its suitability for resource-constrained embedded / mobile devices. In the proposed approach, modeling and recognition of speakers and words are performed using Gaussian Mixture Model (GMM), which has relatively low computational complexity. The inability of GMM to capture the temporal information of speech, which is vital for word recognition, has been overcome through a simple, yet effective adaptation. After evaluating the performance of two alternative architectures, an integrated speaker-and-word recognition system based on text-dependent speaker recognition has been proposed. The system has been ported to a mobile device as an Android application and tested in real-life environment.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automatic Construction of Runtime Monitors for FPGA Based Designs 基于FPGA设计的运行时监视器的自动构建
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.70
Pratibha Sawhney, G. Ganesh, A. Bhattacharjee
{"title":"Automatic Construction of Runtime Monitors for FPGA Based Designs","authors":"Pratibha Sawhney, G. Ganesh, A. Bhattacharjee","doi":"10.1109/ISED.2011.70","DOIUrl":"https://doi.org/10.1109/ISED.2011.70","url":null,"abstract":"The failure of a hardware design may be catastrophic if there is a bug that exhibits during runtime. Such bugs may remain in the implementation due to shortfall in conventional testing and are referred to as corner case bugs. Runtime monitoring of hardware designs used in critical systems is required to take care of corner case bugs. The basic idea behind runtime monitoring is to identify certain critical design invariants and write assertions, which monitor these invariants during runtime. This paper describes a tool that translates properties written in PSL (Property Specification Language) into synthesizable VHDL called as monitors. These monitors can be synthesized along with the actual design. Automata theoretic approach is used for this translation.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124193887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Highly Sensitive ?R/R Measurement System for Nano-electro-Mechanical Cantilever Based Bio-sensors 基于悬臂式纳米机电生物传感器的高灵敏度R/R测量系统
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.36
S. Surya, S. Nag, Avil J. Fernandes, Sahir Gandhi, D. Agarwal, Gaurav Chatterjee, V. Rao
{"title":"Highly Sensitive ?R/R Measurement System for Nano-electro-Mechanical Cantilever Based Bio-sensors","authors":"S. Surya, S. Nag, Avil J. Fernandes, Sahir Gandhi, D. Agarwal, Gaurav Chatterjee, V. Rao","doi":"10.1109/ISED.2011.36","DOIUrl":"https://doi.org/10.1109/ISED.2011.36","url":null,"abstract":"Functionalized piezoresistive nano-electromechanical cantilevers are promising tools for sensor applications. This paper reports an integration of custom fabricated piezoresistive cantilever sensors and sensitive analog front end circuit for detection of bio-markers. The system operates on the principles of nano-meter deflection of cantilever sensors, due to antigen-antibody interactions, which in turn exhibits change in piezoresistance. The instrumentation hardware can measure resistance changes down to 14 parts per million (ppm) and maximum sensitivity is 2.134 V/ppm. Experiments have been performed with 90K? and 1M? base resistances. A wheat stone bridge connected resistors has been used where the functionalized cantilever forms one of the arms. The measured results using this battery operated system has been presented along with calibration technique. The size of this LCD (Liquid crystal display) based system was reduced to fit into a hand held point-of-care form factor. In addition, users can operate this measurement system with the help of computer to connect to the internet. Measurement results are presented with the introduction of bovine serum albumin (BSA) over the cantilever sensors. This demonstrates the possible application for detection of myocardial infarction in clinical settings.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130720471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low Active Power High Speed Cache Design 低有功功率高速缓存设计
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.46
A. Islam, M. Kafeel, A. Imran, M. Hasan
{"title":"Low Active Power High Speed Cache Design","authors":"A. Islam, M. Kafeel, A. Imran, M. Hasan","doi":"10.1109/ISED.2011.46","DOIUrl":"https://doi.org/10.1109/ISED.2011.46","url":null,"abstract":"The active power is one of the major contributors to the total power consumption in the SRAM cell. It consists mainly of two components -- write power and read power. These power dissipations occur due to charging/discharging of large bit line capacitance. On-chip cache size has become increasingly important for high performance applications, and it now presents more of a limit to microprocessor speed than clock rate. The models and methodologies for the design of SRAM, an integral component of microprocessor cache, have changed with time. Presently, continued scaling is threatened by variability in SRAM performance and function. This work addresses the emerging threat of variability keeping active power consumption and speed of operation in consideration.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116897094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DCSFPSS assisted morphological approach for grey twill fabric defect detection and defect area measurement for fabric grading DCSFPSS辅助灰色斜纹织物疵点检测和织物分级缺陷面积测量的形态学方法
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.45
Jayashree Vaddin, S. Subbaraman
{"title":"DCSFPSS assisted morphological approach for grey twill fabric defect detection and defect area measurement for fabric grading","authors":"Jayashree Vaddin, S. Subbaraman","doi":"10.1109/ISED.2011.45","DOIUrl":"https://doi.org/10.1109/ISED.2011.45","url":null,"abstract":"This paper proposes a new optimal morphological filter design using DC suppressed Fourier power spectrum sum (DCSFPSS) plot as a major technique to extract the texture periodicity features of textile fabrics. Periodicity is further used to assist the selection of size of structuring element(SE) for morphological operation(MO) to detect grey twill fabric defects. The performance of the scheme is evaluated on number of homogeneous twill grey fabric images with loose weft and stitch type of defects. Computation of number of defects, area of each defect and total defect area in a given fabric image is estimated. Then a simple binary based defect search algorithm is adopted to determine the presence of defects. The performance parameter of the proposed algorithm is firstly obtained in terms of accuracy of correct defect detection (ACD) which is found to be 98% for stitch and 94.7% for loose weft defect samples of two twill grey fabric classes. Secondly, the recognition of defect area less than 1$mm ^2$, which has not been reported in the literature yet, was possible using this algorithm. Further we propose to use this method to grade the fabric based on standard systems adopted for classifying the fabric. The details of the experimentation and the results thereof are presented in this paper.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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