Low Active Power High Speed Cache Design

Abstract

The active power is one of the major contributors to the total power consumption in the SRAM cell. It consists mainly of two components -- write power and read power. These power dissipations occur due to charging/discharging of large bit line capacitance. On-chip cache size has become increasingly important for high performance applications, and it now presents more of a limit to microprocessor speed than clock rate. The models and methodologies for the design of SRAM, an integral component of microprocessor cache, have changed with time. Presently, continued scaling is threatened by variability in SRAM performance and function. This work addresses the emerging threat of variability keeping active power consumption and speed of operation in consideration.