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Design of Low Power, High Performance FIR Filter Using Modified Differential Evolution Algorithm 基于改进差分进化算法的低功耗高性能FIR滤波器设计
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.58
K. S. Reddy, M. S. Bharath, S. K. Sahoo, S. Sinha, J. Reddy
{"title":"Design of Low Power, High Performance FIR Filter Using Modified Differential Evolution Algorithm","authors":"K. S. Reddy, M. S. Bharath, S. K. Sahoo, S. Sinha, J. Reddy","doi":"10.1109/ISED.2011.58","DOIUrl":"https://doi.org/10.1109/ISED.2011.58","url":null,"abstract":"In digital filters, maximum power consumption occurs during multiplication operations. Hence, to reduce power consumption, the number of multiplications has to be minimized. The number of Signed-Power-of-Two (SPT) terms in the filter coefficients has to be optimally minimized, without compromising on the filter response. A modified Differential Evolution (MDE) algorithm has been used to generate optimized coefficients for digital FIR filters. The filters designed using MDE and the standard Remez (REM) Exchange method are synthesized in 90nm technology and their performances are compared. The critical delay, area and power of MDE implementation are found to improve by 6%, 12% and 16%respectively with respect to REM.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129877283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support 一个完全流水线模块化多精度浮点乘法器与向量支持
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.14
Alok Baluni, Farhad Merchant, S. Nandy, S. Balakrishnan
{"title":"A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support","authors":"Alok Baluni, Farhad Merchant, S. Nandy, S. Balakrishnan","doi":"10.1109/ISED.2011.14","DOIUrl":"https://doi.org/10.1109/ISED.2011.14","url":null,"abstract":"The rapid evolution of reconfigurable computing places a great demand for Floating Point Multipliers (FPMs) capable of supporting wide range of application domains from scientific computing to multimedia applications. While former needs the support of higher precision formats like Double Precision(DP) / Extended Precision(EP), the latter needs Single Instruction Multiple Data (SIMD) feature in Single Precision (SP) mode. This paper presents the design of an FPM catering to both the needs using a hierarchical design approach. The FPM supports nine parallel SP multiplications every cycle with a latency of two cycles and one DP/EP multiplication every cycle with a latency of three cycles. The FPM is architected to support all four IEEE rounding modes. Compared to other FPMs that support multiple precision and SIMD processing, our FPM achieves 9x throughput for vectored SP mode without penalising the throughput for DP/EP modes. This improvement in performance is achieved at a modest cost of 30 percent more area and 11 percent more power. The modular architecture of the proposed FPM results in significant power reduction upto 80 percent for scalar SP mode.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Performance Study of Harmony Search Algorithm for Analog Circuit Sizing 模拟电路尺寸协调搜索算法的性能研究
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.42
Shravan Kudikala, S. L. Sabat, S. Udgata
{"title":"Performance Study of Harmony Search Algorithm for Analog Circuit Sizing","authors":"Shravan Kudikala, S. L. Sabat, S. Udgata","doi":"10.1109/ISED.2011.42","DOIUrl":"https://doi.org/10.1109/ISED.2011.42","url":null,"abstract":"Automation in nominal design of analog circuits considerably reduces the overall time to market of mixed-mode ICs. Application of meta-heuristic optimization algorithms with simulator level fitness evaluation for circuit sizing is a popular automation approach. In this work, with the same approach, we investigate the performance of Harmony Search (HS) algorithm. HS is a relatively new meta-heuristic inspired from musical process, in which population represents memory of a group of musicians, that searches for a perfect state of harmony. Performance of HS is compared with Differential Evolution (DE) algorithm for design of a 180nm CMOS process based Folded Cascode Operational Trans-conductance Amplifier (FCOTA) with continuous time common mode feedback. Results show that, at initial period of iterations, HS converges quickly but fails to converge to the global optimum as compared to DE algorithm.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116443529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads Power - sim:用于估计移动工作负载功率概况的SOC模拟器
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1166/jolpe.2012.1193
Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, N. Bhilegaonkar, P. Dasgupta, C. Mandal, Krishna Paul
{"title":"POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads","authors":"Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, N. Bhilegaonkar, P. Dasgupta, C. Mandal, Krishna Paul","doi":"10.1166/jolpe.2012.1193","DOIUrl":"https://doi.org/10.1166/jolpe.2012.1193","url":null,"abstract":"The power consumption of complex System-On-Chips (SOCs) heavily depends on application profile and usage patterns. Customization of power management strategies based on application as well as user profile have great promise towards minimizing the power wastage. In this paper, we present a methodology for computing the power usage at a higher level of granularity for analyzing the scope of the optimization of the power management strategies in a complex low power SOC with respect to given workload profiles by customizing the boundaries of power domains. The proposed methodology computes the power usage for a given SOC and a given power domain partitioning. We demonstrate the effect of user profiles on the partitioning strategy through a case study.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126493348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Capacity Reversible Data Hiding Using IWT 使用IWT的高容量可逆数据隐藏
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.39
T. Meenpal, A. Bhattacharjee
{"title":"High Capacity Reversible Data Hiding Using IWT","authors":"T. Meenpal, A. Bhattacharjee","doi":"10.1109/ISED.2011.39","DOIUrl":"https://doi.org/10.1109/ISED.2011.39","url":null,"abstract":"This paper presents a novel loss less data hiding scheme for digital images using integer wavelet transform and threshold embedding technique. Data are embedded into the least two significant bit-plane (LSB) of high frequency CDF (2,2) integer wavelet coefficients whose magnitudes are smaller than a certain predefined threshold. Histogram modification is applied as a preprocessing to prevent overflow/underflow. Experimental results show that this scheme outperforms the prior arts in terms of a higher payload and better PSNR with efficient computations.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Adiabatic 5T SRAM 绝热5T SRAM
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.57
Mamatha Samson, Satyam Mandavalli
{"title":"Adiabatic 5T SRAM","authors":"Mamatha Samson, Satyam Mandavalli","doi":"10.1109/ISED.2011.57","DOIUrl":"https://doi.org/10.1109/ISED.2011.57","url":null,"abstract":"In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write operation. This energy efficient SRAM also provides good performance parameters and hence suitable for high density embedded systems.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125937958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Concurrent Dual Band Transmitter for 2.4/5.2GHz Wireless LAN Applications 用于2.4/5.2GHz无线局域网应用的并发双频发射器
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.24
Z. Akhter, N. Pathak
{"title":"Concurrent Dual Band Transmitter for 2.4/5.2GHz Wireless LAN Applications","authors":"Z. Akhter, N. Pathak","doi":"10.1109/ISED.2011.24","DOIUrl":"https://doi.org/10.1109/ISED.2011.24","url":null,"abstract":"The paper reports design of a concurrent dual band transmitter for simultaneous operation at 2.4/5.2GHz. A combination of direct conversion and parallel architectures is utilized to satisfy the requirements of various signal modulation schemes that are employed in wireless local area network. The entire transmitter architecture is implemented using hybrid microwave integrated circuit (HMIC) technology. The system exhibits a maximum data rate of 60-Mbps.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Threshold Read Method for Multi-bit Memristive Crossbar Memory 多位记忆交叉存储器的阈值读取方法
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.68
Y. Yilmaz, P. Mazumder
{"title":"Threshold Read Method for Multi-bit Memristive Crossbar Memory","authors":"Y. Yilmaz, P. Mazumder","doi":"10.1109/ISED.2011.68","DOIUrl":"https://doi.org/10.1109/ISED.2011.68","url":null,"abstract":"Memristors have raised great interest in various logic and non-volatile memory applications. They are especially a good candidate for crossbar memory applications for their capability of being integrated in high densities and low switching power consumptions. In this paper we propose a novel read/write circuitry for memristive crossbar memories that enables reliable multilevel data storage in single cell while eliminating the use of reference resistors thus reducing the number of comparisons required. The proposed method can be used independent of the nonlinear characteristics of the memristive device and it can also be utilized by memory cells incorporating a memristor and series diodes.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Process Variation Tolerant SRAM Cell Design 过程变化容忍SRAM单元设计
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.22
Suresh Kumar Varanasi, S. Mandavilli
{"title":"Process Variation Tolerant SRAM Cell Design","authors":"Suresh Kumar Varanasi, S. Mandavilli","doi":"10.1109/ISED.2011.22","DOIUrl":"https://doi.org/10.1109/ISED.2011.22","url":null,"abstract":"One of the major hurdles in the design of Static Random Access Memory (SRAM) cell is the ever increasing process variations. To counter this researchers have proposed various bit-cell and non-bit-cell oriented designs. However, the proposed techniques require additional circuitry and hence account for large area overhead. In this paper we propose the use of rise time of word-line signal as a measure to reduce the impact of the process variations on the SRAM cells. Simulation results show that using a higher rise time resulted in drastic reduction in the number of cells that fail to read or write. Number of cells that can successfully write or read improved from 82% to 98.2% and 90% to 98.8% respectively. However, there is some speed penalty to achieve this.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134361539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Addressing the Interoperability Issues While Using JPEG-XR 解决使用JPEG-XR时的互操作性问题
2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.31
Harish Yagain, Srinivas Donapati
{"title":"Addressing the Interoperability Issues While Using JPEG-XR","authors":"Harish Yagain, Srinivas Donapati","doi":"10.1109/ISED.2011.31","DOIUrl":"https://doi.org/10.1109/ISED.2011.31","url":null,"abstract":"JPEG XR is a new still-image compression standard projected as the successor of the popular JPEG standard. JPEG-XR surely has several advantages over JPEG in terms of higher dynamic range, image tiling capability and higher compression ratios. However it still needs some time before it is actually deployed and accepted by the imaging community. JPEG standard currently has wide-spread usage right from software utilities for viewing and processing images, to support in browsers and to even having dedicated hardware engines to encode and decode JPEG images. In this paper we try to explore the possibilities of interoperability issues in JPEG-XR usage model with reference to handling of non-standard YUV images. When non-standard YUV images are processed by JPEG-XR encoder and decoder, the image viewers cannot display proper images. Based on the simulation results obtained from this study, we show that the proposed approach can overcome the limitation and enable proper images being viewed. In all, we propose three possible approaches that can be followed to make JPEG-XR deployment a user-friendly experience.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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