A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support

Abstract

The rapid evolution of reconfigurable computing places a great demand for Floating Point Multipliers (FPMs) capable of supporting wide range of application domains from scientific computing to multimedia applications. While former needs the support of higher precision formats like Double Precision(DP) / Extended Precision(EP), the latter needs Single Instruction Multiple Data (SIMD) feature in Single Precision (SP) mode. This paper presents the design of an FPM catering to both the needs using a hierarchical design approach. The FPM supports nine parallel SP multiplications every cycle with a latency of two cycles and one DP/EP multiplication every cycle with a latency of three cycles. The FPM is architected to support all four IEEE rounding modes. Compared to other FPMs that support multiple precision and SIMD processing, our FPM achieves 9x throughput for vectored SP mode without penalising the throughput for DP/EP modes. This improvement in performance is achieved at a modest cost of 30 percent more area and 11 percent more power. The modular architecture of the proposed FPM results in significant power reduction upto 80 percent for scalar SP mode.