2011 International Symposium on Electronic System Design最新文献_第5页

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications 吠陀分频器:高速VLSI应用的新架构(ASIC)

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.62

P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat

引用次数: 25

Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon Interconnects 石墨烯纳米带互连中的串扰和栅氧化可靠性分析

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.54

Debaprasad Das, H. Rahaman

引用次数: 44

Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits 可逆电路缺门故障检测自动测试集的推导

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.69

D. Kole, H. Rahaman, D. K. Das, B. Bhattacharya

引用次数: 7

Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits 基于统计阻塞的纳米cmos算法电路鲁棒性快速估计与补偿方法

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.64

Luo Sun, J. Mathew, D. Pradhan, S. Mohanty

{"title":"Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits","authors":"Luo Sun, J. Mathew, D. Pradhan, S. Mohanty","doi":"10.1109/ISED.2011.64","DOIUrl":"https://doi.org/10.1109/ISED.2011.64","url":null,"abstract":"The challenges for nano-CMOS based design engineers have been aggravated due to the introduction of variability into the design phase. One of the ways to understand the circuit behaviors under process variation is to analyze the rare events that may be originated due to such process variation. A method named Statistical Blockade (SB) has been proposed to estimate the rare events statistics especially for high-replication circuits. It has shown much faster speed than traditional exhaustive Monte Carlo simulation. The full Monte Carlo simulation may estimate the tolerant ability for the designs of different CMOS logic styles by estimating the statistics (e.g. mean, variance, and standard deviation) of the circuit specification. However, it is immensely computationally expensive, can be infeasible for large circuits, and may consume significant man hours in the ever shortening time-to-market. Therefore, the fast robustness comparison for different designs are performed with Intelligent Statistical Blockade (ISB) method. In the ISB method, the tail part of the whole distribution is used in estimation, thereby saving time. In this paper, the ISB method is proposed to compare arithmetic circuits designs. An adder with different logic styles is considered as an example of arithmetic circuit. The novel method with ISB shows much faster than standard Monte Carlo simulation. Furthermore, for the chosen design which is proved to be robust even in worst-case, the optimal body bias voltage is applied to improve the performance and power while reducing the variability with Adaptive Body Bias (ABB) technique.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128440797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL 基于蜂群启发元建模的纳米cmos锁相环快速优化

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.13

Oleg Garitselov, S. Mohanty, E. Kougianos, Priyadarsan Patra

{"title":"Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL","authors":"Oleg Garitselov, S. Mohanty, E. Kougianos, Priyadarsan Patra","doi":"10.1109/ISED.2011.13","DOIUrl":"https://doi.org/10.1109/ISED.2011.13","url":null,"abstract":"The design and optimization complexity of analog/mixed-signal (AMS) components causes significant increase in the design cycle as the technology progresses towards deep nanoscale. This paper presents a two-tier approach to significantly reduce the design cycle time by combining accurate metamodeling and intelligent optimization. The paper first presents metamodeling which is a surrogate model of a parasitic-aware SPICE model of the circuit in order to simplify the optimization calculations and minimize the design space exploration time. The paper then introduces the Bee Colony Optimization (BCO) algorithm for nano-CMOS AMS circuit optimization. To best of the authors' knowledge, this is the first research combining metamodel and BCO for AMS design space exploration. The proposed design optimization flow is used on 5 metamodels with 21 design parameters each, corresponding to 5 distinct Figures of Merit (FoMs) to conduct multi objective optimization. A 180 nm LC-VCO PLL frequency generation circuit is used as case study. The optimization achieved approx. 90% power and 52% jitter reduction while keeping locking time constraints on the system. In comparison to an exhaustive simulation approach, metamodeling is 10^20 times faster.","PeriodicalId":349073,"journal":{"name":"2011 International Symposium on Electronic System Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology 面向规模化技术的超低功耗混合碳纳米管互连性能分析

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.74

S. Pable, M. Hasan, M. Kafeel

引用次数: 3

Energy Efficient Memory Authentication Mechanism in Embedded Systems 嵌入式系统中的节能内存认证机制

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.34

Satyajeet Nimgaonkar, M. Gomathisankaran

引用次数: 6

Versatile Battery Chargers for New Age Batteries 多功能电池充电器的新时代电池

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.71

H. Joshi, M. Baghini

引用次数: 0

A Harmonically Superior Switching Modulator with Wide Baseband and Real-Time Tunability 具有宽基带和实时可调性的谐波优越开关调制器

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.65

H. Patangia, S. Gourisetti

引用次数: 6

Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications 适合移动应用的混合计算平台的性能-功率设计空间探索

2011 International Symposium on Electronic System Design Pub Date : 2011-12-19 DOI: 10.1109/ISED.2011.55

R. Jayaraman, Handi Kartadihardja, D. Maskell

引用次数: 0