Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL

Abstract

The design and optimization complexity of analog/mixed-signal (AMS) components causes significant increase in the design cycle as the technology progresses towards deep nanoscale. This paper presents a two-tier approach to significantly reduce the design cycle time by combining accurate metamodeling and intelligent optimization. The paper first presents metamodeling which is a surrogate model of a parasitic-aware SPICE model of the circuit in order to simplify the optimization calculations and minimize the design space exploration time. The paper then introduces the Bee Colony Optimization (BCO) algorithm for nano-CMOS AMS circuit optimization. To best of the authors' knowledge, this is the first research combining metamodel and BCO for AMS design space exploration. The proposed design optimization flow is used on 5 metamodels with 21 design parameters each, corresponding to 5 distinct Figures of Merit (FoMs) to conduct multi objective optimization. A 180 nm LC-VCO PLL frequency generation circuit is used as case study. The optimization achieved approx. 90% power and 52% jitter reduction while keeping locking time constraints on the system. In comparison to an exhaustive simulation approach, metamodeling is 10^20 times faster.