Low Complexity Flexible Hardware Efficient Decimation Selector

Abstract

Coefficient decimation (CD) is a computationally efficient reconfigurable finite impulse response (FIR) filter method. Reconfigurability is achieved by decimating the fixed coefficient modal (prototype) filter in-order to realize variable bandwidth responses. Reconfigurable decimation selector is a vital part of the CD architecture which allows the user to select different decimation factor of choice. In this paper, we propose a low complexity, efficient hardware architecture for reconfigurable decimation selector. The implementation results in Virtex IV-xc4vsx35-10ff668 FPGA shows that when compared to other decimation selector techniques available in literature, the proposed implementation technique saves up to 5.2% of area and 7.6% of power for a filter order of 101.