Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage

Abstract

The Scan based testing is used for delay testing in sequential circuits and in general it is implemented by using launch-on-capture (LoC) delay tests. Launch-on-shift (LoS) delay tests are usually more efficient to obtain high fault coverage with appreciably lesser number of test vectors, but it requires a fast scan enable, which is not supported by majority of designs. The architecture of scan design limits the two pattern delay tests that can be applied to circuit under test which results in degradation of delay test coverage. The use of enhanced scan flip-flops can improve this problem by facilitating arbitrary delay test vector pairs, at the cost of high area overhead and also requires fast hold signal. This paper presents a new enhanced scan methodology implemented with the slow hold signal. Experimental results on ISCAS'89 benchmark circuit shows improvement in TDF fault coverage for this methodology.