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2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)最新文献

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Time delay digital tanlock loop with linearized phase detector 带线性化鉴相器的延时数字锁相环
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410869
M. Al-Qutayri, S. Al-Araji, O. A. Al-Ali, Nader Anani
{"title":"Time delay digital tanlock loop with linearized phase detector","authors":"M. Al-Qutayri, S. Al-Araji, O. A. Al-Ali, Nader Anani","doi":"10.1109/ICECS.2009.5410869","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410869","url":null,"abstract":"This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the time delay unit of the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output of the inverse tan phase detector. The change in this output is proportional to the changes in the input signal frequency of the system. This results in keeping the quadrature relationship between the two channels that make up the TDTL. This linearization of the phase error detector results in the improvement of the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127656938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 130nm CMOS tunable digital frequency divider for dual-band microwave radiometer 一种用于双频微波辐射计的130nm CMOS可调谐数字分频器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410975
D. Dermit, F. Ducati, Damenico Balsamo, P. Lucchi, M. Borgarino, G. Jacquemod
{"title":"A 130nm CMOS tunable digital frequency divider for dual-band microwave radiometer","authors":"D. Dermit, F. Ducati, Damenico Balsamo, P. Lucchi, M. Borgarino, G. Jacquemod","doi":"10.1109/ICECS.2009.5410975","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410975","url":null,"abstract":"An inductorless, divide-by-256 fixed-modulus digital frequency divider with programmable input sensitivity, fabricated in 130nm CMOS bulk process, is presented. Both the absence of inductors and the architecture used allow to obtain a small sized chip. The fabricated frequency divider exhibits two minima in sensitivity at 4.4GHz and 6.25GHz consuming about 5.4mW from a 1.2V voltage supply. The total active area of the frequency divider is 360×115 µm2.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-cost Bayer to RGB bilinear interpolation with hardware-aware median filter 低成本Bayer到RGB双线性插值与硬件感知中值滤波器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410826
Jesús M. Pérez, P.S. Espeso, M. Martinez
{"title":"Low-cost Bayer to RGB bilinear interpolation with hardware-aware median filter","authors":"Jesús M. Pérez, P.S. Espeso, M. Martinez","doi":"10.1109/ICECS.2009.5410826","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410826","url":null,"abstract":"This High-definition and real-time video is one of the features that is being explored for the next generation of telecommunication systems. Most commercial video-cameras obtain Bayer images that have to be converted to RGB ones. Even though most of these cameras are able to perform this conversion internally, when working with high-definition images this process is quite slow and impedes real-time applications. Therefore, it is interesting to explore high-speed solutions that can perform Bayer to RGB conversion outside the camera. This paper presents a color interpolation design based on bilinear interpolation and a new real-time median filter with low memory requirements. The system is designed for real-time high-definition video systems although it can be used for single frame interpolation. The median filter proposed increases the performance by about 4 dBs with respect to a simple bilinear interpolation system. This improvement in the performance is obtained without adding extra delay or memory to the classical bilinear interpolation. It only increases lightly the area. The memory consumption is reduced to two frame lines and it is implemented in less than 30% of the area available in a Spartan III S500 FPGA, working at almost 100 MHz. The system can work with high resolution frames up to 1280×1024 pixels.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Modelling and analysis of scaled MOSFET devices and circuit simulation 缩放MOSFET器件的建模与分析及电路仿真
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410889
Mustafa M. El-Muradi, Mohamed A. El-Mansouri
{"title":"Modelling and analysis of scaled MOSFET devices and circuit simulation","authors":"Mustafa M. El-Muradi, Mohamed A. El-Mansouri","doi":"10.1109/ICECS.2009.5410889","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410889","url":null,"abstract":"A new approach of extremely scaled MOSFET device based on modified BSIM4v6 is presented for modelling and analysis. The model ensures the continuities of current-voltage, conductance and transconductance through all voltage bias conditions. The improved model has been enhanced by device parameters and dimensions to accounts for all use in various device technologies with less extracted parameters. The accurate model has been implemented in the circuit simulation such as Ring-oscillators and CMOS circuits using HSPICE, SMART Spice and higher level SPICE, comparison with other simulation techniques showed a compromise between computation time and more complex model equations, accuracy is the major factor of simulation results and device performance.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129110283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Q-enhanced LC bandpass filter using CAIRO+ 使用CAIRO+的q增强LC带通滤波器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410763
D. Belfort, N. Beilleau, H. Aboushady, M. Louërat, S. Catunda
{"title":"A Q-enhanced LC bandpass filter using CAIRO+","authors":"D. Belfort, N. Beilleau, H. Aboushady, M. Louërat, S. Catunda","doi":"10.1109/ICECS.2009.5410763","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410763","url":null,"abstract":"In this paper, we present a systematic design procedure for Q-enhanced integrated LC filters, which does not require any simulations and is thus suitable for design automation. The design procedure has been described in the CAIRO+ analog design environment, containing the BSIM3v3 models of the MOS transistors. Precise estimations of the quality factor and the resonance frequency were made possible by adding the integrated inductance ¿-model into the design environment. Several design examples of 2.4 GHz Q-enhanced LC filters are given in a 0.13 ¿m CMOS process.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132414341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
E-Shaped Patch Antenna modeling with MoM and RWG basis functions 基于MoM和RWG基函数的e型贴片天线建模
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410970
N. Ghannay, A. Samet
{"title":"E-Shaped Patch Antenna modeling with MoM and RWG basis functions","authors":"N. Ghannay, A. Samet","doi":"10.1109/ICECS.2009.5410970","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410970","url":null,"abstract":"In this paper, we put the emphasis on the analysis and modeling of an E-Shaped Patch Antenna for wireless communications. This antenna can be designed to provide an Ultra Wide Bandwidth. The Method of Moment is utilized for the analysis. We use the Mixed Potential Integral Equation (MPIE) in conjunction with the Rao, Wilton and Glisson triangular discretization (RWG basis functions). A comprehensive parametric study has been carried out to understand the effects of various dimensional parameters and to optimize the performance of the antenna.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"934 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133545664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of a balanced 8-modulus RNS 平衡8模RNS的设计
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410923
A. Skavantzos, M. Abdallah, T. Stouraitis, D. Schinianakis
{"title":"Design of a balanced 8-modulus RNS","authors":"A. Skavantzos, M. Abdallah, T. Stouraitis, D. Schinianakis","doi":"10.1109/ICECS.2009.5410923","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410923","url":null,"abstract":"In this paper the design of a balanced 8-modulus RNS system is presented. This RNS is based on the modulus set A = {2<sup>n−5</sup> − 1, 2<sup>n−3</sup> − 1, 2<sup>n−3</sup> + 1, 2<sup>n−2</sup> + 1, 2<sup>n−1</sup> − 1, 2<sup>n−1</sup> + 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}; n = 2k, k = 4, 5, 6, …, which comprises non co-prime moduli. The system is balanced, in the sense that adjacent moduli are of similar word length and achieve fast internal processing and dynamic ranges larger than 32 bits. Its weighted-to-RNS converter is an efficient two-level converter. Its RNS-to-weighted converter is a three-level converter based on a combination of an efficient Chinese Remainder Theorem (CRT), the Mixed Radix Conversion (MRC) technique and an efficient implementation of a 2-channel CRT based on non co-prime moduli.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116702027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A new RC design for mixed-grain based dynamically reconfigurable architectures 一种新的基于混合颗粒的动态可重构结构RC设计
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410843
E. Rhod, L. Sterpone, L. Carro
{"title":"A new RC design for mixed-grain based dynamically reconfigurable architectures","authors":"E. Rhod, L. Sterpone, L. Carro","doi":"10.1109/ICECS.2009.5410843","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410843","url":null,"abstract":"Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132456200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multithread RISC architecture based on programmable interleaved pipelining 基于可编程交错流水线的多线程RISC体系结构
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410802
A. Pułka, A. Milik
{"title":"Multithread RISC architecture based on programmable interleaved pipelining","authors":"A. Pułka, A. Milik","doi":"10.1109/ICECS.2009.5410802","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410802","url":null,"abstract":"The paper deals with problems of design of complex electronic devices with predictable timing. The original solution of multithread interleaved pipelined architecture with programmable length of threads is proposed. The appropriate HDL models of main core (RISC based processor) and interleave controller are discussed. The experiments presenting problem of priorities, time length of threads, deadlines control, switching between threads, and control of the access to the memory are analyzed and discussed.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator 基于CSA-CPA组合累加器的卷积计算在FPGA上的高效映射
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410903
C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata
{"title":"Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator","authors":"C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata","doi":"10.1109/ICECS.2009.5410903","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410903","url":null,"abstract":"In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133435037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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