Multithread RISC architecture based on programmable interleaved pipelining

Abstract

The paper deals with problems of design of complex electronic devices with predictable timing. The original solution of multithread interleaved pipelined architecture with programmable length of threads is proposed. The appropriate HDL models of main core (RISC based processor) and interleave controller are discussed. The experiments presenting problem of priorities, time length of threads, deadlines control, switching between threads, and control of the access to the memory are analyzed and discussed.