C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata
{"title":"基于CSA-CPA组合累加器的卷积计算在FPGA上的高效映射","authors":"C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata","doi":"10.1109/ICECS.2009.5410903","DOIUrl":null,"url":null,"abstract":"In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator\",\"authors\":\"C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata\",\"doi\":\"10.1109/ICECS.2009.5410903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.\",\"PeriodicalId\":343974,\"journal\":{\"name\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"volume\":\"174 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2009.5410903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2009.5410903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator
In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.