基于CSA-CPA组合累加器的卷积计算在FPGA上的高效映射

C. D. Moreno-Moreno, F. Quiles, M. Ortiz, M. Brox, J. Hormigo, J. Villalba, E. Zapata
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引用次数: 7

摘要

在本文中,我们提出了一些处理基于进位保存加法器的快速卷积计算的架构,并打算在fpga上具体实现。由于FPGA具有快速的进位传播路径,因此在FPGA实现中不常用存进位加法器。本文证明了在FPGA上使用存进算法进行卷积运算是可行的。利用FPGA的特殊结构,设计了一种优化的累加器,该累加器可以在相同的硬件条件下处理免进位加和传播进位加。这导致了CSA-CPA的高效组合架构,具有快速计算和优化硬件成本。在不同字长下的实验结果验证了我们的建议。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator
In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.
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