{"title":"一种新的基于混合颗粒的动态可重构结构RC设计","authors":"E. Rhod, L. Sterpone, L. Carro","doi":"10.1109/ICECS.2009.5410843","DOIUrl":null,"url":null,"abstract":"Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A new RC design for mixed-grain based dynamically reconfigurable architectures\",\"authors\":\"E. Rhod, L. Sterpone, L. Carro\",\"doi\":\"10.1109/ICECS.2009.5410843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.\",\"PeriodicalId\":343974,\"journal\":{\"name\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"volume\":\"155 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2009.5410843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2009.5410843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new RC design for mixed-grain based dynamically reconfigurable architectures
Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.