{"title":"低成本Bayer到RGB双线性插值与硬件感知中值滤波器","authors":"Jesús M. Pérez, P.S. Espeso, M. Martinez","doi":"10.1109/ICECS.2009.5410826","DOIUrl":null,"url":null,"abstract":"This High-definition and real-time video is one of the features that is being explored for the next generation of telecommunication systems. Most commercial video-cameras obtain Bayer images that have to be converted to RGB ones. Even though most of these cameras are able to perform this conversion internally, when working with high-definition images this process is quite slow and impedes real-time applications. Therefore, it is interesting to explore high-speed solutions that can perform Bayer to RGB conversion outside the camera. This paper presents a color interpolation design based on bilinear interpolation and a new real-time median filter with low memory requirements. The system is designed for real-time high-definition video systems although it can be used for single frame interpolation. The median filter proposed increases the performance by about 4 dBs with respect to a simple bilinear interpolation system. This improvement in the performance is obtained without adding extra delay or memory to the classical bilinear interpolation. It only increases lightly the area. The memory consumption is reduced to two frame lines and it is implemented in less than 30% of the area available in a Spartan III S500 FPGA, working at almost 100 MHz. The system can work with high resolution frames up to 1280×1024 pixels.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Low-cost Bayer to RGB bilinear interpolation with hardware-aware median filter\",\"authors\":\"Jesús M. Pérez, P.S. Espeso, M. Martinez\",\"doi\":\"10.1109/ICECS.2009.5410826\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This High-definition and real-time video is one of the features that is being explored for the next generation of telecommunication systems. Most commercial video-cameras obtain Bayer images that have to be converted to RGB ones. Even though most of these cameras are able to perform this conversion internally, when working with high-definition images this process is quite slow and impedes real-time applications. Therefore, it is interesting to explore high-speed solutions that can perform Bayer to RGB conversion outside the camera. This paper presents a color interpolation design based on bilinear interpolation and a new real-time median filter with low memory requirements. The system is designed for real-time high-definition video systems although it can be used for single frame interpolation. The median filter proposed increases the performance by about 4 dBs with respect to a simple bilinear interpolation system. This improvement in the performance is obtained without adding extra delay or memory to the classical bilinear interpolation. It only increases lightly the area. The memory consumption is reduced to two frame lines and it is implemented in less than 30% of the area available in a Spartan III S500 FPGA, working at almost 100 MHz. The system can work with high resolution frames up to 1280×1024 pixels.\",\"PeriodicalId\":343974,\"journal\":{\"name\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2009.5410826\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2009.5410826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
摘要
这种高清晰度和实时视频是下一代电信系统正在探索的功能之一。大多数商用摄像机获得的拜耳图像必须转换为RGB图像。尽管大多数相机能够在内部执行这种转换,但在处理高清图像时,这个过程相当缓慢,并且阻碍了实时应用。因此,探索能够在相机外实现拜耳到RGB转换的高速解决方案是很有趣的。本文提出了一种基于双线性插值的彩色插值设计和一种低内存要求的实时中值滤波器。虽然该系统可以用于单帧插值,但它是为实时高清视频系统设计的。所提出的中值滤波器相对于简单的双线性插值系统提高了约4 db的性能。这种性能的提高是在不增加额外的延迟或内存的情况下获得的。它只是稍微增加了面积。内存消耗减少到两条帧线,并且在Spartan III S500 FPGA中实现的可用面积不到30%,工作频率接近100 MHz。该系统可以使用高达1280×1024像素的高分辨率帧。
Low-cost Bayer to RGB bilinear interpolation with hardware-aware median filter
This High-definition and real-time video is one of the features that is being explored for the next generation of telecommunication systems. Most commercial video-cameras obtain Bayer images that have to be converted to RGB ones. Even though most of these cameras are able to perform this conversion internally, when working with high-definition images this process is quite slow and impedes real-time applications. Therefore, it is interesting to explore high-speed solutions that can perform Bayer to RGB conversion outside the camera. This paper presents a color interpolation design based on bilinear interpolation and a new real-time median filter with low memory requirements. The system is designed for real-time high-definition video systems although it can be used for single frame interpolation. The median filter proposed increases the performance by about 4 dBs with respect to a simple bilinear interpolation system. This improvement in the performance is obtained without adding extra delay or memory to the classical bilinear interpolation. It only increases lightly the area. The memory consumption is reduced to two frame lines and it is implemented in less than 30% of the area available in a Spartan III S500 FPGA, working at almost 100 MHz. The system can work with high resolution frames up to 1280×1024 pixels.