Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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Project management and design methodology support for the Cave Project: a hyperdocument-centric approach Cave项目的项目管理和设计方法支持:以超文档为中心的方法
L. Indrusiak, R. Reis
{"title":"Project management and design methodology support for the Cave Project: a hyperdocument-centric approach","authors":"L. Indrusiak, R. Reis","doi":"10.1109/SBCCI.1999.803117","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803117","url":null,"abstract":"The Cave Project is a research effort aiming to make possible the distribution of CAD resources over the World Wide Web. This distribution is intended to be user-transparent, so the network locations of the resources are hidden by the hypermedia structure of the WWW environment. This paper describes the advantages of using hypermedia to model design flow, proposing the navigation over a chain of hyperdocuments instead successive invocation of tools. The paper also describes the current research and development on project management, a key point in network based design environments, since the design teams are usually distributed.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126823815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A tool for analysis of universal logic gates functionality 通用逻辑门功能分析工具
F.G. de Lima, M. Johann, J. Guntzel, L. Carro, R. Reis
{"title":"A tool for analysis of universal logic gates functionality","authors":"F.G. de Lima, M. Johann, J. Guntzel, L. Carro, R. Reis","doi":"10.1109/SBCCI.1999.803116","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803116","url":null,"abstract":"This paper presents a general methodology to determine the number of NPN functions of a programmable cell. This methodology was implemented in a tool called Programa-de-TV that is able to implement all NPN operations over n-input lookup tables. This work also shows a comparison between developed Universal Logic Gates (ULGs). One application of this technique is to select an appropriate programmable ULG to implement FPGA or Masked Programmable Architectures, according to some cost criteria. Another application of this tool is to help technology mapping into ULGs using an n-LUT mapper.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126945155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design for testability reuse in synthesis for testability 为可测试性而设计,在可测试性的综合中重用
P. Bukovjan, M. Marzouki, W. Maroufi
{"title":"Design for testability reuse in synthesis for testability","authors":"P. Bukovjan, M. Marzouki, W. Maroufi","doi":"10.1109/SBCCI.1999.803123","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803123","url":null,"abstract":"This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testability, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be proposed by the system, considering the available components in the library and the possibility of generating additional testability structures. The cost/quality trade-off is also based on the result of the testability analysis process.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131683444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power optimization using dynamic power management 使用动态电源管理进行电源优化
J. Monteiro
{"title":"Power optimization using dynamic power management","authors":"J. Monteiro","doi":"10.1109/SBCCI.1999.803105","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803105","url":null,"abstract":"Power dissipation has recently emerged as one the most critical design constraints. A wide range of techniques has already been proposed for the optimization of logic circuits for low power. Power management methods are among the most effective techniques for power reduction. These methods detect periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. Several methods have been presented that perform shut-down on a clock-cycle base. Depending on the input conditions at the beginning of a clock-cycle, the clock driving some of the registers in the circuit can be inhibited, thus reducing the switching activity in the fanout of those registers. These techniques are referred to as data-dependent or dynamic power management techniques. In this tutorial we describe some of the most representative data-dependent power management techniques that have recently been proposed, namely: precomputation, guarded evaluation, gated-clock finite state machines (FSM)'s and FSM decomposition. Each of these techniques uses a different approach to identify the input conditions for which the circuit (or part of) can be disabled. These techniques are put into perspective and recent results are discussed.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Multilevel finite difference methods for the characterization of substrate coupling in deep sub-micron designs 表征深亚微米设计中衬底耦合的多能级有限差分方法
L. Silveira, N. Vargas
{"title":"Multilevel finite difference methods for the characterization of substrate coupling in deep sub-micron designs","authors":"L. Silveira, N. Vargas","doi":"10.1109/SBCCI.1999.802961","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802961","url":null,"abstract":"Accurate modeling of noise coupling effects due to crosstalk via the substrate is an increasingly important concern for the design and verification of analog, digital and mixed analog-digital systems. In this paper we present a technique for model characterization that is based on a finite difference formulation whose solution is accelerated by means of a multilevel method. This technique can be used for accurate and efficient extraction of substrate coupling parameters in deep sub-micron designs.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A binary-tree architecture for scheduling real-time systems with hard and soft tasks 一种用于调度具有硬任务和软任务的实时系统的二叉树结构
S. Sáez, Joan Vila
{"title":"A binary-tree architecture for scheduling real-time systems with hard and soft tasks","authors":"S. Sáez, Joan Vila","doi":"10.1109/SBCCI.1999.802972","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802972","url":null,"abstract":"Complex real-time systems are required to jointly schedule both periodic and aperiodic tasks. To do this, optimal schedulers are dynamic slack stealing algorithms (DSS). However, these software schedulers are impractical due to their large overheads that always result in delays and reduced CPU utilization. One of the proposed solutions to this problem is doing scheduling in hardware. This paper analyzes in depth a hardware design based on binary trees.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116133609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 9-bit parallel pipelined multiplier based on the 3-bit recoding from Booth's algorithm 基于布斯算法的3位重编码的9位并行流水线乘法器
L. Caldeira, T. Pimenta, E. Cotrim
{"title":"A 9-bit parallel pipelined multiplier based on the 3-bit recoding from Booth's algorithm","authors":"L. Caldeira, T. Pimenta, E. Cotrim","doi":"10.1109/SBCCI.1999.802974","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802974","url":null,"abstract":"This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as \"possible\" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124449460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit-level considerations for mixed signal programmable components 混合信号可编程元件的电路级考虑
L. Carro
{"title":"Circuit-level considerations for mixed signal programmable components","authors":"L. Carro","doi":"10.1109/SBCCI.1999.803098","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803098","url":null,"abstract":"This paper presents some architectural studies regarding mixed signal programmable components (FPGAs or gate arrays). The effect of programmability through the use of switches is analyzed, and it is shown that the result is a transfer function modification when real characteristics of the switches are assumed. Moreover, the paper proposes the use of externally linear, internally nonlinear analog circuits, since this procedure could eliminate the error introduced by the switches. Using this approach, analog area is greatly reduced, and circuits can be built on top of digital technologies. Some experimental results in the analog and digital domain support the proposed approach to mixed circuit reprogrammability, being the basis for a mixed signal FPGA.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High speed FIR filters for digital decimation 用于数字抽取的高速FIR滤波器
M. Brambilla, D. Guidi, V. Liberali
{"title":"High speed FIR filters for digital decimation","authors":"M. Brambilla, D. Guidi, V. Liberali","doi":"10.1109/SBCCI.1999.803103","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803103","url":null,"abstract":"This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in /spl Sigma//spl Delta/ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"82 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126024574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Advanced compact model for the charges and capacitances of short-channel MOS transistors 短沟道MOS晶体管电荷和电容的先进紧凑模型
O. da Costa Gouveia-Filho, M. C. Schneider, C. Galup-Montoro
{"title":"Advanced compact model for the charges and capacitances of short-channel MOS transistors","authors":"O. da Costa Gouveia-Filho, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/SBCCI.1999.802959","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802959","url":null,"abstract":"This paper presents a new compact model for the intrinsic charges and (trans) capacitances of the MOSFET including short-channel effects such as drain induced barrier lowering (DIBL), channel length modulation (CLM) and carrier velocity saturation. Explicit and compact expressions for charges and (trans) capacitances valid in all regimes of operation are presented. Simulations examples that illustrate short-channel effects in charges and (trans) capacitances are shown.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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