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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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An approach for microsystems codesign 一种微系统协同设计方法
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802965
R. Ribas, F. Behrens
{"title":"An approach for microsystems codesign","authors":"R. Ribas, F. Behrens","doi":"10.1109/SBCCI.1999.802965","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802965","url":null,"abstract":"The increasing interest in microsystems technology or MEMS (Micro-Electro-Mechanical Systems) is a result of the progress in the integrated circuit (IC) fabrication domain, in the last decades. Nowadays, a great effort is being made to construct non-electrical parts on a single chip in order to obtain monolithic multi-functional smart sensors. For this, the CAD tools must also support such a multi-domain design environment, including from system behavior description and simulation to a unified layout construction. An approach to microsystems codesign is presented, and some back-end tools (layout level) such as layout generators, cross-section and 3D viewers, and etching simulators are already available.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114206013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Estimating functional unit number in the PISH codedesign system by using Petri nets 用Petri网估计PISH码设计系统中的功能单元数
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802962
Paulo Maciel, E. Barros, Wolfgang Rosenstiel
{"title":"Estimating functional unit number in the PISH codedesign system by using Petri nets","authors":"Paulo Maciel, E. Barros, Wolfgang Rosenstiel","doi":"10.1109/SBCCI.1999.802962","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802962","url":null,"abstract":"This work presents two approaches for computing the number of functional units in the PISH hardware/software codesign system. The proposed methods use Petri net as common formalism for performing quantitative analysis. The use of Petri net permits us to use a specification non-dependent partitioning method. Particularly, the Petri net as an intermediate format allows to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper is devoted to describing those approaches, but an overview of the general hardware/software codesign method is also presented.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"373 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133761111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Comparison between quasi-uniform linear cellular automata and linear feedback shift registers as test pattern generators for built-in self-test applications 准一致线性元胞自动机与线性反馈移位寄存器作为内置自检应用测试模式生成器的比较
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803121
P. S. Cardoso, Michael Strum, J. Amazonas, W. Chau
{"title":"Comparison between quasi-uniform linear cellular automata and linear feedback shift registers as test pattern generators for built-in self-test applications","authors":"P. S. Cardoso, Michael Strum, J. Amazonas, W. Chau","doi":"10.1109/SBCCI.1999.803121","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803121","url":null,"abstract":"Linear feedback shift registers (LFSRs) and cellular automata (CA) are well known structures that generate pseudo-random vector sequences. Quasi-Uniform Linear Cellular Automata (QULCA) were shown to be the simplest (most uniform) CAs capable of generating maximum length sequences. In this paper we compare the performance between two types of QULCA, called QULCA90 and QULCA150, and two particular types of LFSRs, namely, QULFSR/sub MIN/ and QULFSR/sub MAX/. They present respectively the minimum and maximum number of EXOR gates in their feedback path, while still generating maximum length sequences. These four types of structures present good characteristics when used as TPGs in a high level synthesis environment for Built-in Self-Testable (BIST) applications. The comparison was based on the area overhead required to generate each structure and on the test length required to achieve a given Fault Coverage (FC). The well known ISCAS 85 benchmark circuits were used in our work. We show that in most cases the QULCA present superior performance than the better known LFSRs while not consuming much more area.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133460247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Microprocessors for the years 2001 and 2008: Where will we be in 2001? What will still need to be done for 2008? 2001年和2008年的微处理器:2001年我们会在哪里?2008年还需要做些什么?
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802955
Y. Patt
{"title":"Microprocessors for the years 2001 and 2008: Where will we be in 2001? What will still need to be done for 2008?","authors":"Y. Patt","doi":"10.1109/SBCCI.1999.802955","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802955","url":null,"abstract":"Summary form only given, as follows. There seems to be no end to the higher and higher performance expected of future generations of microprocessors. By the year 2001, process technology will provide 100 million transistors on a single silicon die, and by the year 2008, one billion transistors. Our job: to harness these transistors on behalf of higher performance. Performance is always about delivering instruction bandwidth to the core, and then consuming that bandwidth. That means very wide issue machines, combined with what it takes to support them. In this talk, we will discuss the major challenges to delivering high instruction bandwidth, and the major challenges to consuming that bandwidth, and what we are doing about them. We will look at our two most recent activities: a very aggressive Trace Cache and Subordinate Simultaneous Microthreading. Finally, we will look at some of what remains to be done, and what that will look like in the microprocessor of the year 2008.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121949086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test escapes: analysis of short defect 测试逃逸:短缺陷分析
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803111
M. Renovell, F. Azdis, Y. Bertrand
{"title":"Test escapes: analysis of short defect","authors":"M. Renovell, F. Azdis, Y. Bertrand","doi":"10.1109/SBCCI.1999.803111","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803111","url":null,"abstract":"This paper analyzes the different types of test escape with the final objective to propose a solution to minimize some of the test escapes. Using a simple example of short defect in the context of Boolean testing, it is first demonstrated that the defect behavior depends on unpredictable parameters. It is shown that a defect may be detectable with a vector but for a given domain of the unpredictable parameter called the Detection Domain. Using the concept of Detection Domain, 3 different types of test escape are identified. It is then demonstrated that one type of test escape can be minimized using 'Improved fault models'.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124219931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A FPGA version of a non-linear adaptive filter 非线性自适应滤波器的FPGA版本
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803104
D. Franco, L. Carro
{"title":"A FPGA version of a non-linear adaptive filter","authors":"D. Franco, L. Carro","doi":"10.1109/SBCCI.1999.803104","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803104","url":null,"abstract":"This paper presents the study of a non-linear adaptive filter implementation using VHDL, targeted to FPGA devices. The paper presents the basic structure of the filter, as well as a discussion on the area and speed results with different multipliers. A full 8-tap filter was synthesized with different architecture choices.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114174836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Specification and design of an Ethernet interface soft IP 以太网接口软IP的规范与设计
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803125
J. Fragoso, E. C. Pereira, Juergen Rochol, S. Bampi, R. Reis
{"title":"Specification and design of an Ethernet interface soft IP","authors":"J. Fragoso, E. C. Pereira, Juergen Rochol, S. Bampi, R. Reis","doi":"10.1109/SBCCI.1999.803125","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803125","url":null,"abstract":"The IP (intellectual property) for Ethernet interface is a hardware module designed to execute the MAC (media access control) service on the Ethernet standard. The goal of this IP module is to provide an easy way to develop new devices with connection to an Ethernet LAN (local area network). The standard protocols used make this IP module reusable for different designs with an interface to Ethernet LANs. The Ethernet Interface IP is described and simulated in VHDL.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Interface design and refinement using state-based techniques 使用基于状态的技术进行接口设计和改进
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802970
H. Klapuri, J. Takala, J. Saarinen
{"title":"Interface design and refinement using state-based techniques","authors":"H. Klapuri, J. Takala, J. Saarinen","doi":"10.1109/SBCCI.1999.802970","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802970","url":null,"abstract":"We describe how a state-based model is used to specify embedded systems and achieve successful interface designs. We consider two approaches to implementing hardware-software interfaces. The first approach is a conventional one, modifying only one of the two components with incremental refinements by superposition. The second approach focuses on the interface itself so that coarse-grained interactions can be replaced by implementable fine-grained interactions and refinement formulas. As our specification formalism we use Lamport's Temporal Logic of Actions.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129013589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimum design of MOS amplifiers MOS放大器的优化设计
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802967
R. Pinto, M. C. Schneider, C. Galup-Montoro
{"title":"Optimum design of MOS amplifiers","authors":"R. Pinto, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/SBCCI.1999.802967","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802967","url":null,"abstract":"This paper presents a design procedure for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. It is shown that in most cases there is an optimum bias in moderate inversion for which the attainable DC gain is maximum. The design and measurements on a common-source amplifier illustrate the appropriateness of the proposed methodology.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Solving satisfiability in combinational circuits with backtrack search and recursive learning 用回溯搜索和递归学习求解组合电路的可满足性
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803118
Joao Marques-Silva, L. Guerra e Silva
{"title":"Solving satisfiability in combinational circuits with backtrack search and recursive learning","authors":"Joao Marques-Silva, L. Guerra e Silva","doi":"10.1109/SBCCI.1999.803118","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803118","url":null,"abstract":"Boolean Satisfiability (SAT) is a widely used modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, equivalence checking and circuit delay computation, among many other problems. This paper starts by describing how Boolean Satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Afterwards, it shows how recursive learning techniques can be incorporated into Boolean Satisfiability algorithms. The proposed algorithmic framework has several natural applications in EDA. Moreover, potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean Satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained, on a large number of benchmark examples in different problem domains, illustrate the effectiveness of the proposed techniques.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124627334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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