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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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Codesign system performance based on memory configurations 基于内存配置协同设计系统性能
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802963
L. M. Mourelle, N. Nedjah
{"title":"Codesign system performance based on memory configurations","authors":"L. M. Mourelle, N. Nedjah","doi":"10.1109/SBCCI.1999.802963","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802963","url":null,"abstract":"In the codesign methodology, the system specification is partitioned into hardware and software subsystems. Subsequently the former is synthesised into custom hardware, while the latter is compiled into processor code. A common target architecture is based on a shared bus uing a single-port global memory. Therefore, the system performance is compromised by bus contention. The hardware and software subsystems communicate through either a busy-wait or an interrupt mechanism. This paper presents two alternatives for memory configuration: one uses a dual-port memory to substitute the original single-port shared memory of the target architecture and the other uses a cache memory for the hardware subsystem, while keeping the single-port shared memory. The dual-port memory configuration aims to avoid to contention, whereas the cache memory configuration aims to reduce bus contention during the hardware subsystem memory accesses. The objective of this study is to achieve an acceptable performance in terms of the overall execution time of an application.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Testing semiconductor chips: trends and solutions 测试半导体芯片:趋势和解决方案
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803128
Y. Zorian
{"title":"Testing semiconductor chips: trends and solutions","authors":"Y. Zorian","doi":"10.1109/SBCCI.1999.803128","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803128","url":null,"abstract":"As system-on-chip (SOC) complexity and the move to very deep submicron (VDSM) technology pushes the threshold of semiconductor technology, conventional test methods become inadequate and costly. This new level of complexity demands that designers alter the way they approach chip development in order to keep up with diminishing time-to-market requirements and stay within budgets. Embedded test enables customers to produce higher-quality products in less time. The use of embedded test raises margins and significantly reduces the time required for system verification test and debug. The speaker will address chip- and board-level signal integrity issues, system architecture design, business (time to market), embedded systems (design considerations for embedded systems, testing real-time systems, systems integration), test (high-density design issues, mixed-signal testing, digital testing issues, test technologies-IDDQ, SCAN, design for testability), SOC integration/test issues-making SOC a reality, and the importance of embedded test and front-end (time to money, quality and cost).","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124003528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Covering strategies for library free technology mapping 涵盖图书馆免费技术映射的策略
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803115
A. Reis
{"title":"Covering strategies for library free technology mapping","authors":"A. Reis","doi":"10.1109/SBCCI.1999.803115","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803115","url":null,"abstract":"This paper compares dynamic methodologies for technology mapping targeting virtual libraries available through cell generators. Dynamic covering is reputed for being exact, but in fact its exactness depends on the ordering of the initial subject description. A new dynamic approach exploiting reordering of the initial description is proposed and compared to the traditional dynamic approach from SIS. The approach we propose is exact with respect to the number of multi-input complex gates. Main contributions are the description of the effect of reordering and the comparison between the approaches. A tool dedicated to library free technology mapping has been implemented to demonstrate the significance of the method.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133492480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Criteria for static current estimation: how good are they? An approach incorporating IC quality requirements 静态电流估计的标准:它们有多好?集成电路质量要求的方法
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803113
F. Vargas, M. Nicolaidis
{"title":"Criteria for static current estimation: how good are they? An approach incorporating IC quality requirements","authors":"F. Vargas, M. Nicolaidis","doi":"10.1109/SBCCI.1999.803113","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803113","url":null,"abstract":"This paper presents a novel approach to estimate the I/sub DDQ/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, our approach proposes the characterization of the faulty circuit quiescent current with respect to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, such as the minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133863862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SCOB, a soft-core for the Blowfish cryptographic algorithm SCOB，河豚加密算法的软核
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803126
Sérgio L. C. Salom ̃ao, João M. S. de Alcântara, Vladimir C. Alves, Antônio C. C. Vieira
{"title":"SCOB, a soft-core for the Blowfish cryptographic algorithm","authors":"Sérgio L. C. Salom ̃ao, João M. S. de Alcântara, Vladimir C. Alves, Antônio C. C. Vieira","doi":"10.1109/SBCCI.1999.803126","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803126","url":null,"abstract":"Data security is an important issue in today's computer networks. Several emerging applications require secure data channels over open networks. At the same time, the bandwidth of data channels is rapidly increasing, as demonstrated by current ATM networks. In this scenario, data communication products now have to incorporate high-performance security devices. This paper presents SCOB, a soft-core implementation of the Blowfish cryptographic algorithm. This soft-core is oriented towards applications demanding a high throughput and exploits both the spatial and the temporal parallelism available in the Blowfish algorithm. An ASIC implementation of SCOB in 0.7 /spl mu/m two-metal layer CMOS technology, reaches up to 266 Mbps at 66 MHz, while an FPGA implementation provided up to 40 Mbps at 10 MHz.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system 行为的快速硬件编译成基于fpga的动态可重构计算系统
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803109
João MP Cardoso, H. Neto
{"title":"Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system","authors":"João MP Cardoso, H. Neto","doi":"10.1109/SBCCI.1999.803109","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803109","url":null,"abstract":"This paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). These new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with predefined architectures. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. The algorithms under development are being integrated onto an HW compiler that accepts programs previously compiled to Java/sup TM/ Bytecodes. A series of experiments has been performed using a number of practical examples and the results achieved so far are very promising and indicate that the RW compilation techniques proposed can provide significant improvements over currently available methods.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115304212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On-line test of a switching circuit 开关电路的在线测试
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803114
J.A. Bastos, J.A. Kussler, L.J. Cassol, M. Lubaszewski
{"title":"On-line test of a switching circuit","authors":"J.A. Bastos, J.A. Kussler, L.J. Cassol, M. Lubaszewski","doi":"10.1109/SBCCI.1999.803114","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803114","url":null,"abstract":"This paper presents the use of partial duplication to on-line test a switching circuit used in a communication system. The test methodology is validated by fault simulation. The final system is fault tolerant because a test cell may replace a faulty cell, whenever diagnosis can be successfully carried out. A prototype of the on-line testable switching circuit has been produced.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116265721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing a Java microcontroller to specific applications 针对特定应用设计一个Java微控制器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802958
S. A. Ito, L. Carro, R. Jacobi
{"title":"Designing a Java microcontroller to specific applications","authors":"S. A. Ito, L. Carro, R. Jacobi","doi":"10.1109/SBCCI.1999.802958","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802958","url":null,"abstract":"Stack machines are known to provide code compactness and simple execution engines-important features when implementing small devices. This paper discusses some benefits, problems and open questions by using a stack based microcontroller to support native execution of Java bytecode. The discussion is based on our experience in designing a Java ASIP in FPGA, in order to explore software compatibility, reconfiguration capability and the small size of optimized microcontrollers to implement specific applications. The paper also presents the synthesized machine architecture and shows some area and speed results.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122035323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A low sensitivity switched-capacitor filter design with testability features 具有可测试性的低灵敏度开关电容滤波器设计
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803100
J. M. Cañive, J. Gomes, A. Petraglia
{"title":"A low sensitivity switched-capacitor filter design with testability features","authors":"J. M. Cañive, J. Gomes, A. Petraglia","doi":"10.1109/SBCCI.1999.803100","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803100","url":null,"abstract":"The very low sensitivity properties of a switched-capacitor structure based on a parallel connection of two allpass filters has been recently demonstrated by computer simulations. This paper presents the IC design of an SC video filter using this technique, and shows experimental results obtained in the laboratory to verify the validity of the proposed approach. A procedure for testing the transfer function of SC filters based on a parallel connection of allpass filter sections is presented.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133792176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An approach for interface generation in the PISH co-design system PISH协同设计系统中的接口生成方法
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802969
C. Araujo, E. Barros
{"title":"An approach for interface generation in the PISH co-design system","authors":"C. Araujo, E. Barros","doi":"10.1109/SBCCI.1999.802969","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802969","url":null,"abstract":"This paper describes a methodology for interface generation in the PISH co-design system, which allows the hardware/software co-design of concurrent processes described in Occam. The hardware/software partitioning generates a description including processes to be implemented in software, processes to run in hardware and processes for communication purposes. This new description is generated by applying algebraic transformation rules according the results of a cost analysis based on clustering techniques. This strategy preserves the semantics of the initial description. All of these are generated from the initial description in a constructive and correct way.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133870528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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