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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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System synthesis and processor selection in the S/sup 3/E/sup 2/S environment S/sup 3/E/sup 2/S环境下的系统综合与处理器选择
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803108
L. Carro, M. Kreutz, F. Wagner, M. Oyamada
{"title":"System synthesis and processor selection in the S/sup 3/E/sup 2/S environment","authors":"L. Carro, M. Kreutz, F. Wagner, M. Oyamada","doi":"10.1109/SBCCI.1999.803108","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803108","url":null,"abstract":"This paper presents the synthesis technique available in S/sup 3/E/sup 2/S, a CAD environment to specify, simulate, and synthesize electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. S/sup 3/E/sup 2/S is based on a distributed, object-oriented system model, where abstract objects are initially used to express complex behavior and may be later refined into digital or analog hardware and software. Finally, system synthesis is targeted to a set of complex processors, which can be either custom designed or off-the-shelf components. The environment selects processors that best match the desired application by analyzing processor and application characteristics. The paper explains the architecture selection process with some examples.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125454446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Testing semiconductor chips: trends and solutions 测试半导体芯片:趋势和解决方案
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803128
Y. Zorian
{"title":"Testing semiconductor chips: trends and solutions","authors":"Y. Zorian","doi":"10.1109/SBCCI.1999.803128","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803128","url":null,"abstract":"As system-on-chip (SOC) complexity and the move to very deep submicron (VDSM) technology pushes the threshold of semiconductor technology, conventional test methods become inadequate and costly. This new level of complexity demands that designers alter the way they approach chip development in order to keep up with diminishing time-to-market requirements and stay within budgets. Embedded test enables customers to produce higher-quality products in less time. The use of embedded test raises margins and significantly reduces the time required for system verification test and debug. The speaker will address chip- and board-level signal integrity issues, system architecture design, business (time to market), embedded systems (design considerations for embedded systems, testing real-time systems, systems integration), test (high-density design issues, mixed-signal testing, digital testing issues, test technologies-IDDQ, SCAN, design for testability), SOC integration/test issues-making SOC a reality, and the importance of embedded test and front-end (time to money, quality and cost).","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124003528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MCA: a single chip one-port scalable ATM layer controller MCA:单片单端口可扩展ATM层控制器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802975
J. D. de Lima, Elmar U. K. Melchier, A.C. Cavalcanti
{"title":"MCA: a single chip one-port scalable ATM layer controller","authors":"J. D. de Lima, Elmar U. K. Melchier, A.C. Cavalcanti","doi":"10.1109/SBCCI.1999.802975","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802975","url":null,"abstract":"This work proposes a flexible microprogrammable controller to perform the ATM layer functions of an ATM switch. The controller has as main characteristic the flexibility to implement several algorithm types, by changing microinstruction programming only. The description and functionalities of the main blocks that compose its architecture are presented as well final synthesis, simulations and layout results of a \"standard-cells\" MCA's ASIC implementation. Finally the architecture of an ATM switch based on independent MCA's and its scalability and reusability are showed.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129453739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 0.25 /spl mu/m CMOS injection locked 5.6 Gb/s clock and data recovery cell 一个0.25 /spl mu/m的CMOS注入锁定5.6 Gb/s的时钟和数据恢复单元
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802973
T. Gabara
{"title":"An 0.25 /spl mu/m CMOS injection locked 5.6 Gb/s clock and data recovery cell","authors":"T. Gabara","doi":"10.1109/SBCCI.1999.802973","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802973","url":null,"abstract":"The harmonic clock signals in a 5.6 Gb/s NRZ (Non Return to Zero) 2/sup 7/-1 pseudo-random data stream are used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is deserialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. This architecture offers power savings since the data and clock rate are reduced immediately by a factor of two. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6 Gb/s is achieved using a conventional 0.25 /spl mu/m CMOS technology.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SCOB, a soft-core for the Blowfish cryptographic algorithm SCOB，河豚加密算法的软核
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803126
Sérgio L. C. Salom ̃ao, João M. S. de Alcântara, Vladimir C. Alves, Antônio C. C. Vieira
{"title":"SCOB, a soft-core for the Blowfish cryptographic algorithm","authors":"Sérgio L. C. Salom ̃ao, João M. S. de Alcântara, Vladimir C. Alves, Antônio C. C. Vieira","doi":"10.1109/SBCCI.1999.803126","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803126","url":null,"abstract":"Data security is an important issue in today's computer networks. Several emerging applications require secure data channels over open networks. At the same time, the bandwidth of data channels is rapidly increasing, as demonstrated by current ATM networks. In this scenario, data communication products now have to incorporate high-performance security devices. This paper presents SCOB, a soft-core implementation of the Blowfish cryptographic algorithm. This soft-core is oriented towards applications demanding a high throughput and exploits both the spatial and the temporal parallelism available in the Blowfish algorithm. An ASIC implementation of SCOB in 0.7 /spl mu/m two-metal layer CMOS technology, reaches up to 266 Mbps at 66 MHz, while an FPGA implementation provided up to 40 Mbps at 10 MHz.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system 行为的快速硬件编译成基于fpga的动态可重构计算系统
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803109
João MP Cardoso, H. Neto
{"title":"Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system","authors":"João MP Cardoso, H. Neto","doi":"10.1109/SBCCI.1999.803109","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803109","url":null,"abstract":"This paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). These new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with predefined architectures. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. The algorithms under development are being integrated onto an HW compiler that accepts programs previously compiled to Java/sup TM/ Bytecodes. A series of experiments has been performed using a number of practical examples and the results achieved so far are very promising and indicate that the RW compilation techniques proposed can provide significant improvements over currently available methods.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115304212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On-line test of a switching circuit 开关电路的在线测试
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803114
J.A. Bastos, J.A. Kussler, L.J. Cassol, M. Lubaszewski
{"title":"On-line test of a switching circuit","authors":"J.A. Bastos, J.A. Kussler, L.J. Cassol, M. Lubaszewski","doi":"10.1109/SBCCI.1999.803114","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803114","url":null,"abstract":"This paper presents the use of partial duplication to on-line test a switching circuit used in a communication system. The test methodology is validated by fault simulation. The final system is fault tolerant because a test cell may replace a faulty cell, whenever diagnosis can be successfully carried out. A prototype of the on-line testable switching circuit has been produced.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116265721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing a Java microcontroller to specific applications 针对特定应用设计一个Java微控制器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802958
S. A. Ito, L. Carro, R. Jacobi
{"title":"Designing a Java microcontroller to specific applications","authors":"S. A. Ito, L. Carro, R. Jacobi","doi":"10.1109/SBCCI.1999.802958","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802958","url":null,"abstract":"Stack machines are known to provide code compactness and simple execution engines-important features when implementing small devices. This paper discusses some benefits, problems and open questions by using a stack based microcontroller to support native execution of Java bytecode. The discussion is based on our experience in designing a Java ASIP in FPGA, in order to explore software compatibility, reconfiguration capability and the small size of optimized microcontrollers to implement specific applications. The paper also presents the synthesized machine architecture and shows some area and speed results.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122035323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A low sensitivity switched-capacitor filter design with testability features 具有可测试性的低灵敏度开关电容滤波器设计
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803100
J. M. Cañive, J. Gomes, A. Petraglia
{"title":"A low sensitivity switched-capacitor filter design with testability features","authors":"J. M. Cañive, J. Gomes, A. Petraglia","doi":"10.1109/SBCCI.1999.803100","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803100","url":null,"abstract":"The very low sensitivity properties of a switched-capacitor structure based on a parallel connection of two allpass filters has been recently demonstrated by computer simulations. This paper presents the IC design of an SC video filter using this technique, and shows experimental results obtained in the laboratory to verify the validity of the proposed approach. A procedure for testing the transfer function of SC filters based on a parallel connection of allpass filter sections is presented.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133792176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An approach for interface generation in the PISH co-design system PISH协同设计系统中的接口生成方法
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802969
C. Araujo, E. Barros
{"title":"An approach for interface generation in the PISH co-design system","authors":"C. Araujo, E. Barros","doi":"10.1109/SBCCI.1999.802969","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802969","url":null,"abstract":"This paper describes a methodology for interface generation in the PISH co-design system, which allows the hardware/software co-design of concurrent processes described in Occam. The hardware/software partitioning generates a description including processes to be implemented in software, processes to run in hardware and processes for communication purposes. This new description is generated by applying algebraic transformation rules according the results of a cost analysis based on clustering techniques. This strategy preserves the semantics of the initial description. All of these are generated from the initial description in a constructive and correct way.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133870528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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