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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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Semiconductor knowledge management and soft-core reuse 半导体知识管理与软核复用
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803124
S. Olcoz
{"title":"Semiconductor knowledge management and soft-core reuse","authors":"S. Olcoz","doi":"10.1109/SBCCI.1999.803124","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803124","url":null,"abstract":"A soft-cores design reuse methodology requires a hierarchical database approach and a new wave of specific tools for exploiting them in heterogeneous and network distributed frameworks. The differences between soft-cores, particularly VHDL ones, and software-like build and reuse processes set up the platform for proposing the VHDL-ICE environment as one feasible solution for an adequate adoption of the proposed approach. The availability of frameworks like this for supporting EDA on the Internet will ease the establishment of a mature adoption of soft-core design reuse in the intranets and the Internet, as part of a semiconductor knowledge management policy.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A bit scalable architecture for fuzzy processors 模糊处理器的可扩展架构
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802957
R. d'Amore, K. Heinz Kienitz, O. Saotome
{"title":"A bit scalable architecture for fuzzy processors","authors":"R. d'Amore, K. Heinz Kienitz, O. Saotome","doi":"10.1109/SBCCI.1999.802957","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802957","url":null,"abstract":"Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. This paper presents bit scalable architecture that allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description. The size of the internal units is defined from a small number of parameters in the highest level entity.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"4 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134470787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Register files constraint satisfaction during scheduling of DSP code DSP代码调度过程中寄存器文件约束的满足
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802971
C. A. Pinto, B. Mesman, Koen van Eijk
{"title":"Register files constraint satisfaction during scheduling of DSP code","authors":"C. A. Pinto, B. Mesman, Koen van Eijk","doi":"10.1109/SBCCI.1999.802971","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802971","url":null,"abstract":"Algorithms in digital signal processing (DSP) impose tight timing constraints that the compiler has to respect while considering the limited capacity of the available register files in a target DSP processor. Traditional code generation methods that schedule spill code to satisfy storage capacity may take many iterations and are usually not capable of satisfying the timing constraints. In this paper we present a new method to handle register file capacity constraints during scheduling. The method identifies potential bottlenecks for register binding and subsequently serializes the lifetimes of values until it can be guaranteed that all capacity constraints will be satisfied after scheduling. Experiments show that we efficiently obtain high quality instruction schedules for DSP kernels.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115738417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An architect's workbench for reconfigurable computing 架构师用于可重构计算的工作台
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803110
R. Skliarova, A. Ferrari
{"title":"An architect's workbench for reconfigurable computing","authors":"R. Skliarova, A. Ferrari","doi":"10.1109/SBCCI.1999.803110","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803110","url":null,"abstract":"This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124854897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of radiation on digital architectures: one year results from a satellite experiment 辐射对数字建筑的影响:一年的卫星实验结果
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803112
R. Velazco, P. Cheynet, R. Ecoffet
{"title":"Effects of radiation on digital architectures: one year results from a satellite experiment","authors":"R. Velazco, P. Cheynet, R. Ecoffet","doi":"10.1109/SBCCI.1999.803112","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803112","url":null,"abstract":"Twenty-four experiments on-board a scientific satellite, successfully launched by Naval Research Laboratories, are operating in a high radiation environment since November 1997. Two of these experiments, designed by TIMA in collaboration with CNES (French Space Agency) were programmed to provide evidences of Artificial Neural Network intrinsic fault tolerance properties. This paper presents conclusions issued of the analysis of more than one year telemetred data.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"951 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementing a self-testing 8051 microprocessor 实现了一个自测试的8051微处理器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803122
É. Cota, M. R. Krug, M. Lubaszewski, L. Carro, A. Susin
{"title":"Implementing a self-testing 8051 microprocessor","authors":"É. Cota, M. R. Krug, M. Lubaszewski, L. Carro, A. Susin","doi":"10.1109/SBCCI.1999.803122","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803122","url":null,"abstract":"This work presents the preliminary results obtained for the high level implementation of a self-testing 8051 microprocessor. From an existing VHDL description of the microprocessor, six main blocks were identified: a state generation block, a control unit, a validation block, an ALU, a RAM and a ROM. For five of them, a test strategy was studied and implemented, so that the whole circuit embedded test structures capable of performing the microprocessor test at-speed. In this paper, we present the test strategies used and the implementation results achieved from a synthesis process in a FPGA environment.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128768953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware/software specification, design and test using a system level approach 硬件/软件规格，设计和测试使用系统级方法
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802964
O. P. Dias, J. Semião, C. Pereira, I. Teixeira, J. P. Teixeira
{"title":"Hardware/software specification, design and test using a system level approach","authors":"O. P. Dias, J. Semião, C. Pereira, I. Teixeira, J. P. Teixeira","doi":"10.1109/SBCCI.1999.802964","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802964","url":null,"abstract":"The purpose of this paper is to present an environment that allows the reliable, in-time system specification and design of complex hardware/software (HW/SW) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. Three different tools are available, SIMOO, a CASE tool is used during analysis and specification phases, and as a simulator after architecture generation. SysObj is used for architecture generation and quality assessment. Test-Adder is used for architecture reconfiguration in order to incorporate Design For Testability (DFT) techniques. A case study (a design of soft wrappers for a PIC embedded core in a SOC (System-on-a-Chip)) is used to ascertain the usefulness of the environment.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126275425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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