模糊处理器的可扩展架构

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI:10.1109/SBCCI.1999.802957

R. d'Amore, K. Heinz Kienitz, O. Saotome

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引用次数: 4

摘要

为了满足实时需求，已经提出了几种实现模糊处理器的硬件架构，但很少有适合自动合成的硬件架构。本文提出了一种可以自动合成不同位宽分辨率模糊处理器的位可伸缩结构。合成是由VHDL描述完成的。内部单元的大小由最高级实体中的少量参数定义。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A bit scalable architecture for fuzzy processors

Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. This paper presents bit scalable architecture that allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description. The size of the internal units is defined from a small number of parameters in the highest level entity.

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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)

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