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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)最新文献

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Conductances and noise in trapezoidal association of transistors for analog applications using a SOT methodology [in CMOS] 使用SOT方法模拟应用的晶体管梯形组合中的电导和噪声[在CMOS中]
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802960
JungBum Choi, S. Bampi
{"title":"Conductances and noise in trapezoidal association of transistors for analog applications using a SOT methodology [in CMOS]","authors":"JungBum Choi, S. Bampi","doi":"10.1109/SBCCI.1999.802960","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802960","url":null,"abstract":"This paper presents results on comparisons and advantages that allow mixed analog-digital circuit design on SOT (sea-of-transistors) array methodology. The aim is to present the advantages of using a suitable trapezoidal association of digital transistors, to improve the output conductance. Noise considerations are also presented to further justify the need for several transistors in the association, improving the characteristic noise of short-channel transistors. Several structures of TAT (trapezoidal association of transistors) and single transistors of electrically equivalent sizes were implemented to allow better comparison and to evaluate noise performance. The SOT unit transistors are on a fixed-size array and experimental results obtained are herein shown for 1.0 /spl mu/m digital technology.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129448555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A multi-functional cell for CMOS analog applications in low-voltage 一种用于低电压CMOS模拟应用的多功能电池
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802966
Chi-Hung Lin, T. Pimenta, M. Ismail, L. Caldeira
{"title":"A multi-functional cell for CMOS analog applications in low-voltage","authors":"Chi-Hung Lin, T. Pimenta, M. Ismail, L. Caldeira","doi":"10.1109/SBCCI.1999.802966","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802966","url":null,"abstract":"This paper describes how to implement three basic CMOS analog cells for low-voltage applications. The three analog cells were obtained from the same basic core cell. The cells are a V-I converter of high precision, a squarer circuit and a multiplier circuit. The core cell presents an almost rail-to-rail differential-input signal and a very low signal distortion. The THD of the core cell is less than 1% for a 3 V. The input signal of the core cell is in the form of a differential voltage and the output is in the form of current. The multiplier is implemented using two modified V-I converters. These basic analog cells can find a wide range of applications in signal processing circuits and communication circuits among others.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121392634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Odd-order current-mode lowpass filters with finite zeros 具有有限零的奇阶电流模式低通滤波器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802968
F. Gálvez-Durand
{"title":"Odd-order current-mode lowpass filters with finite zeros","authors":"F. Gálvez-Durand","doi":"10.1109/SBCCI.1999.802968","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802968","url":null,"abstract":"A novel analogue continuous-time current-mode filter synthesis technique is proposed based on transformed set of state-equations that allow the utilization of only current-mode integrators; current-mode gyrators specifically designed are not necessary. The technique has been successfully used for synthesizing a 5th order lowpass elliptic filter from a passive doubly loaded ladder prototype. Only grounded capacitors are necessary; all floating capacitors and inductors are replaced with active simulations. Small-signal analyses have shown this filter performs well, preserving the low sensitivity inherent to the passive ladder prototype.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125616071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Micro-architecture estimation of the useless power consumption of a high-performance processor 高性能处理器无用功耗的微架构估计
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802956
E. Musoll
{"title":"Micro-architecture estimation of the useless power consumption of a high-performance processor","authors":"E. Musoll","doi":"10.1109/SBCCI.1999.802956","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802956","url":null,"abstract":"The purpose of this work is to evaluate the useless power consumption of a micro-processor that is, the power dissipated to perform those tasks that are not useful for the ultimate goal of committing instructions. This is a first-order estimation of the useless power consumption. A generic high-performance processor is divided in its basic micro-architecture blocks and the amount of useful and useless accesses to each of these blocks is estimated through simulations. The useless power consumption is further divided into useless power when: (a) executing instructions within a mispredicted path, and (b) then executing instructions that will be eventually committed by some of the block accesses performed by these instructions are not needed. The simulations performed indicate that if the useless power dissipation of a high-performance processor could be totally removed (at the cost of no IPC degradation), the overall processor power consumption would be reduced by as much as 65% compared to the same processor in which all the blocks are accessed every cycle.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic and high level synthesis for communication protocols 通信协议的逻辑和高级综合
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803107
R. Lima, E. Carli, A. Pedroza, L. Pirmez, A.C. de Mesquita
{"title":"Logic and high level synthesis for communication protocols","authors":"R. Lima, E. Carli, A. Pedroza, L. Pirmez, A.C. de Mesquita","doi":"10.1109/SBCCI.1999.803107","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803107","url":null,"abstract":"This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols through logic and high level synthesis (HLS). The implementation results of different description styles of protocols and a comparison of the protocol implementation using the HLS technique with a standard cells library and the implementation using a Programmable Logic Device (PLD) are presented. The results include area analysis and clock frequency evaluation of the synthesized hardware.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134195535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault detection in systems with 2nd order dynamics using transient analysis 基于暂态分析的二阶动态系统故障检测
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803099
J. Calvano, Vladimir Castro Alves, M. Lubaszewski
{"title":"Fault detection in systems with 2nd order dynamics using transient analysis","authors":"J. Calvano, Vladimir Castro Alves, M. Lubaszewski","doi":"10.1109/SBCCI.1999.803099","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803099","url":null,"abstract":"This work proposes a transient analysis method for fault detection in systems with 2nd Order dynamics using a functional fault model. The approach considers the system pole-zero configuration as its main characteristic and its correspondence with the peak time and the system overshoot is used in order to detect the faults. The input stimulus is a compact test vector which consists of a step, ramp or parabola. The results show that for this sort of circuit 100% of faults can be detected.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133197874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Symbolic model checking in practice 实践中的符号模型检验
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803097
S. Campos
{"title":"Symbolic model checking in practice","authors":"S. Campos","doi":"10.1109/SBCCI.1999.803097","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803097","url":null,"abstract":"Symbolic model checking is a technique for verifying finite state reactive systems that has been very successful in practice. In this method a system being verified is represented by a state transition graph. Efficient search algorithms are used to determine if the model satisfies properties expressed as temporal logic formulas. The internal representation of the model checker uses binary decision diagrams-BDD, an extremely compact representation of Boolean formulas. Because of the BDD representation it is possible to verify extremely large and complex systems, such as aircraft controllers or robotic controllers, the PCI local bus and the Futurebus+ protocols. This work presents the method and discusses how it can be applied in practice.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"35 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133489326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
MCA: a single chip one-port scalable ATM layer controller MCA:单片单端口可扩展ATM层控制器
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802975
J. D. de Lima, Elmar U. K. Melchier, A.C. Cavalcanti
{"title":"MCA: a single chip one-port scalable ATM layer controller","authors":"J. D. de Lima, Elmar U. K. Melchier, A.C. Cavalcanti","doi":"10.1109/SBCCI.1999.802975","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802975","url":null,"abstract":"This work proposes a flexible microprogrammable controller to perform the ATM layer functions of an ATM switch. The controller has as main characteristic the flexibility to implement several algorithm types, by changing microinstruction programming only. The description and functionalities of the main blocks that compose its architecture are presented as well final synthesis, simulations and layout results of a \"standard-cells\" MCA's ASIC implementation. Finally the architecture of an ATM switch based on independent MCA's and its scalability and reusability are showed.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129453739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 0.25 /spl mu/m CMOS injection locked 5.6 Gb/s clock and data recovery cell 一个0.25 /spl mu/m的CMOS注入锁定5.6 Gb/s的时钟和数据恢复单元
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.802973
T. Gabara
{"title":"An 0.25 /spl mu/m CMOS injection locked 5.6 Gb/s clock and data recovery cell","authors":"T. Gabara","doi":"10.1109/SBCCI.1999.802973","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.802973","url":null,"abstract":"The harmonic clock signals in a 5.6 Gb/s NRZ (Non Return to Zero) 2/sup 7/-1 pseudo-random data stream are used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is deserialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. This architecture offers power savings since the data and clock rate are reduced immediately by a factor of two. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6 Gb/s is achieved using a conventional 0.25 /spl mu/m CMOS technology.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System synthesis and processor selection in the S/sup 3/E/sup 2/S environment S/sup 3/E/sup 2/S环境下的系统综合与处理器选择
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI: 10.1109/SBCCI.1999.803108
L. Carro, M. Kreutz, F. Wagner, M. Oyamada
{"title":"System synthesis and processor selection in the S/sup 3/E/sup 2/S environment","authors":"L. Carro, M. Kreutz, F. Wagner, M. Oyamada","doi":"10.1109/SBCCI.1999.803108","DOIUrl":"https://doi.org/10.1109/SBCCI.1999.803108","url":null,"abstract":"This paper presents the synthesis technique available in S/sup 3/E/sup 2/S, a CAD environment to specify, simulate, and synthesize electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. S/sup 3/E/sup 2/S is based on a distributed, object-oriented system model, where abstract objects are initially used to express complex behavior and may be later refined into digital or analog hardware and software. Finally, system synthesis is targeted to a set of complex processors, which can be either custom designed or off-the-shelf components. The environment selects processors that best match the desired application by analyzing processor and application characteristics. The paper explains the architecture selection process with some examples.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125454446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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